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Verify the connections and, if necessary, try the other
COM port. (Note that you must have a clock applied to
the ADC Evaluation board during this communication
verification stage. Check to make sure that either an
external clock or the TTL oscillator is installed, and that
LED6 is on at reduced intensity.) Once you get a proper
exit from this step, you are ready to configure the capture
board. Right click on the capture control panel, then left
click on 

 

“Configure Capture.”

 

 You will see the following

screen: 

To configure the capture board for direct capture of a con-
tiguous 32k point record of ADC output codes, click on
the selections shown above. Left click on 

 

“Capture

Debug”

 

 and select 

 

“Upper 18 Bits.”

 

 The names of these

selections may seem rather cryptic when you are simply
capturing ADC data. The label names are derived from
functions in the DRCS and CLC5902, so they might
seem out of context for ADC capture uses. Don’t worry
about the label names, just make sure you have selected
the modes as shown above. Then click on 

 

“OK.”

 

   

One final configuration remains. You need to tell the
program  where to store your data. Right click on the
capture control panel, then left click on 

 

“Change Data

File.”

 

 You will see the following menu: 

By left clicking on the little box to the right of the text entry
window, you can select any disk, directory, and file name
that suits you. However, we recommend that you start
with the default file name and location shown. Click on

 

“Default”

 

 and then on 

 

“OK”

 

. If you do not have a

C:\temp directory, please make one. The reason for this
is that the Matlab script files for data analysis look auto-
matically for the file 

 

C:\temp\data.dat

 

. If you wish to

store the data elsewhere, you will need to modify the
Matlab m-files to look for your data file in a different loca-
tion. Obviously, if you are using your own software for
data analysis this is not a concern. 

 

Capture Data!

 

We are finally ready to capture data from the ADC. As a
final check, you can move the mouse until it is on top of
the progress bar (the big bar on the data capture control
panel that now reads (0%). You should see a little yellow
box appear that confirms your capture settings. 

Now, simply left-click on the 

 

“Start”

 

 button on the capture

control panel to start the process. You will see LED 2 light
up on the board, and the bar at the top of the capture
control panel will show the progress of the data transfer.
At 52MSPS, the 32768 samples are collected in only 630
microseconds; the rest of the time is the serial port trans-
fer. Typical times for this transfer are on the order of 10 to
15 seconds. To analyze the data using the Matlab Mfiles
that we have provided, please start Matlab at this time. To
include the provided script files in your Matlab path, type
the following command at the Matlab command prompt: 

 

>> path(path,’c:\nsc\mfiles’)

 

Alternatively, you can change directories at the Matlab
prompt until this is the current directory. From the Matlab
command prompt, type 

 

“analysis_menu”

 

. This will bring

up the following menu: 

Summary of Contents for CLC-CAPT-PCASM

Page 1: ...s Receiver Transmitter an oscillator and a level translator IC The captured data is stored in either three 32K x 8 static RAMs organized into 24 bit words or in a FIFO containing 32K 18 bit words LEDs provide a visual indication of activity DIP switches and a jumper configure several capture functions Section II Capturing Data from ADC Evaluation Boards Getting Started To use the Data Capture boar...

Page 2: ...on board An amplitude of 10 to 16dBm is recommended Here again the HP 8644B is a good choice Software 1 National Semiconductor Software All of the required software is provided on a CD ROM To install the software now insert the CD ROM into your computer and follow the directions The default installation copies all of the files to a directory called c nsc The data capture software is called capture...

Page 3: ...ion board pin 20B The third jumper block J2 is unused Data Capture Board Block Diagram DIP Switches Five of the eight DIP switches are used to configure several capture functions as follows DIP switch 1 This DIP switch specifies whether a Diversity Receiver Evaluation Board or an ADC Evaluation Board is attached to the Data Capture Board ON ADC Evaluation Board is attached Captured data is aligned...

Page 4: ...he Data Capture Board is powered up and the FPGA is initialized it is on to indicate that the board is ready After all the SRAM data has been output it is off LED 2 This LED is on when captured data is available to be output to the serial port After all the data has been output it is off LED 6 This LED is connected to the clock signal selected by DIP switch 1 When the clock is toggling it will be ...

Page 5: ...you start with the default file name and location shown Click on Default and then on OK If you do not have a C temp directory please make one The reason for this is that the Matlab script files for data analysis look auto matically for the file C temp data dat If you wish to store the data elsewhere you will need to modify the Matlab m files to look for your data file in a different loca tion Obvi...

Page 6: ... configuration menu Select Histogram Debug as shown above and click on OK When the data capture control panel returns you can verify your capture settings by positioning the mouse over the progress bar You will see the following display When you press Start now the SRAM will be cleared and then the board will count the number of times each code is output When any count reaches the number that you ...

Page 7: ... and Capture Board combination require 5V at 1A 4 An IBM Compatible Personal Computer running Windows 95 Windows 98 or Windows NT with a serial port capable of 115 200 baud 5 Serial data cable to connect the data capture board to the PC 6 Low noise filtered IF Signal source for analog input to DRCS 7 OPTIONAL Low jitter clock source 10 16dBm sinewave if DRCS crystal oscillator is removed Software ...

Page 8: ...ion The SRAM is useful for displaying time records of data or collecting contiguous blocks of slower data that have been decimated by the CLC5902 DDC The SRAM is the memory element used for the board s hardwired histogram data generation Capture Board Hardware Configuration Options for DRCS data capture Place the WCLK FIFO write clock jumper in the PIN 120 position the VCORE should be in the 5V po...

Page 9: ...arted Next is a discussion of the Mode functions and the related sub functions MODES There are four primary modes in which to run the data capture system each with its own associated options 1 Capture mode configures the Capture Board for data reception from the DRCS evaluation board Both serial and the parallel output ports can be used as the source data path a The 24 Bits option captures serial ...

Page 10: ...ata source The DRCS Debug data will be displayed at the 15 bit resolution limit this is also the case for the DRCS 24 bit Serial Out data and the histogram will be centered about 16 384 assuming there is no intentional DC offset The following figure displays the sine wave histo gram data of the DRCS output generated by the Capture Board at an input frequency of 150MHz and 16dBm in amplitude using ...

Page 11: ...nditions The main portion of the noise power is contained in the carrier s immediate sidebands 5KHz Another point of interest is that there are several spectral lines about 75dBFS and 25KHz on either side of the fundamental These have been traced to the ground loop created by the PC serial interface Both serial interface cables were connected while this data was being collected Removing the cable ...

Page 12: ...e variable to 0 Setting the Dither variable excludes a lower portion of the spectrum from the FFT analysis and is intended to be used in conjunction with a base band dither signal being present at the ADC analog input 12 bit FFT b12_FFT m is the script intended for data analysis in conjunction with the CLC5956 Evaluation Boards DNL_INL dnl_inl m is the script intended for data analysis of the hist...

Page 13: ...13 http www national com CLC CAPT PCASM Evaluation Board Layer 1 CLC CAPT PCASM Evaluation Board Layer 2 CLC CAPT PCASM Evaluation Board Layer 3 CLC CAPT PCASM Evaluation Board Layer 4 ...

Page 14: ...1 1 1 1 1 6 287 287 287 1 9 9 1 1 1 1 1 1 1 6 6 287 9 9 9 9 5 9 9 9 9 1 4 5 2 2 5 1 57 4 4 9 4 3 3 1 1 5 5 1 2 9 1 4 1 4 602 9 4 1 4 4 4 4 4 4 9 4 4 1 4 4 1 4 56 1 1 1 1 1 865 21 B 21 6 7 7 7 7 7 7 7 7 B B B 1 B 1 B 1 B 1 9B2 1 17 1 17 1 17 1 17 1 17 1 17 1 17 1 17 1 17 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 7B 21 06 06 1 1 2 1 21 1 6 1 9B 5 156 167 786 17567 1 6 1B 1B 1B 1B 1B 1B 1B 1B...

Page 15: ...to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax 49 0 180 530 85 86 13th Floor Straight Block Tel 81 043 299 2309 Arlington TX 76017 E mail europe supp...

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