background image

1.

Perform steps 1, 2 and 5 of section 5.2.1.1, above.

9.

With the mouse, you may click and drag to select a
portion  of  the  displayed  waveform  for  better
examination.

2.

Monitor  the  ADC08200  output  at  96-pin  connector
J1 pins B16 through B19 and C16 through C19 (see
appendix for pin assignments).

10. Click on the FFT icon or type 

ALT

, P, F or 

CTRL

-F to

calculate  the  FFT  of  the  data  and  display  a
frequency domain plot.

4.

Clock the data out with a TTL clock of any speed up
to 200 MHz at pin B15 of 96-pin connector J1.

The  FFT  data  will  provide  a  measurement  of  SINAD,
SNR,  THD  and  SFDR,  easing  the  performance
verification of the ADC08200. Note that the readings may
not 

accurately 

reflect 

the 

ADC08200's 

actual

performance unless an input filter is used, as explained in
sections  4.1  and  5.0,  and  unless  the  sampling  is
coherent, as explained below.

5.2.2 Quick Check of Analog Functions

Refer to Figure 1  for  locations  of  connectors,  test  points
and  jumpers  on  the  board.  If  at  any  time  the  expected
response  is  not  obtained,  see  section  5.2.6  on
Troubleshooting.

1.

Perform  steps  1  through  6  (steps  3  and  4  are
optional here) of Section 5.2.1.1.

5.2.4 Getting Consistent Readings

2.

Checl  for  the  presence  of  correct  d.c.  voltages  at
power connector J4, as called for in section 4.6.

Artifacts  can  result  when  we  perform  an  FFT  on  a
digitized  waveform,  producing  inconsistent  results  when
testing repeatedly. The presence of these artifacts means
that  the  ADC  under  test  may  perform  better  than  the
measurements would indicate.

3.

Check TP7 or either terminal of L1 for the presence
of a voltage between 2.7V and 3.3V.

4.

JP1 - Short the two pins closest to Q1 (pins 2  &  3)
to NOT divide the on-board clock oscillator by 2.

5.

Adjust RV1 for a voltage of 1.87V to 1.93V at TP2.

We  can  eliminate  the  need  for  windowing  and  get  more
consistent results if we observe the proper ratios between
the  input  and  sampling  frequencies.  This  greatly
increases the spectral resolution of the  FFT,  allowing  us
to more accurately evaluate the spectral response of the
A/D  converter.  When  we  do  this,  however,  we  must  be
sure  that  the  input  signal  has  high  spectral  purity  and
stability  and  that  the  sampling  clock  signal  is  extremely
stable with minimal jitter.

6.

Adjust RV2 for a voltage of 0.27V to 0.33V at TP4.

7.

Adjust  the  signal  source  at  Analog  Input  J3  for  a
signal  amplitude  of  approximately  1.6VP-P  and

check for the presence of that signal at TP1.

This  completes  the  testing  of  the  analog  portion  of  the
evaluation board.

5.2.3 Quick Check of Software and Computer
Interface Operation

Coherent  sampling  of  a  periodic  waveform  occurs  when
an integer number of cycles exists in the sample window.
The  relationship  between  the  number  of  cycles  sampled
(CY), the number of samples taken (SS), the signal input
frequency  (fin)  and  the  sample  rate  (fs),  for  coherent

sampling, is

1.

Perform steps 1 through 5 of Section 5.2.1.1, above.

2.

Supply a 1.6Vp-p sine  wave  of  1  MHz  to  50MHz  at
Analog Input BNC J3.

3.

Be  sure  there  is  an  interconnecting  cable  between
the board and your computer serial port.

CY
SS

f

in

f

s

=

4.

R

UN

 program WAVEVSN2.EXE.

5.

After turning on the power, be sure to wait for yellow
LED  D4  on  the  Digital  Interface  Board  to  go  out
(about  5  seconds)  before  trying  to  acquire  data  or
the board will "freeze" and you will have to cycle the
power.

CY, the number of cycles in the data record, must be an
integer  number  and  SS,  the  number  of  samples  in  the
data  record,  must  be  a  factor  of  2  integer.  For  optimum
results, CY should also be a prime number.

Further, fin (signal input frequency) and fs (sampling rate)

should  be  locked  to  each  other.  If  they  come  from  the
same  generator,

 

whatever  frequency  instability  (jitter)  is

present in the two signals will cancel each other.

6.

Acquire data by clicking on the ACQUIRE icon or by
pressing 

ALT

, P, A or 

CTRL

-X. Data transfer can take

a few seconds.

7.

When transfer is complete, the data window should
show  many  sine  waves.  The  display  may  show  a
nearly solid area of red, which is O.K.

Windowing (an FFT Option under WaveVision) should be
turned off for coherent sampling.

8.

Double  click  on  the  data  window  and  change  the
"Sampling  Rate  of  this  data  (MHz)"  to  200.  This
must  be  done  each  time  another  data  capture  is
done or the frequency information in the FFT will not
be correct.

5.2.5 Jumper Information

Table 1 indicates the function and use of the jumpers on
the  ADC08200  evaluation  board.  JP2,  JP7  and  JP8  are
hard-wired for 2 memory chips.

8

          http://www.national.com

Summary of Contents for ADC08200

Page 1: ... Semiconductor December 2005 Rev 7 Evaluation Board Instruction Manual ADC08200 8 Bit 10 MSPS to 230 Msps Analog to Digital Converter with Internal Sample Hold 2001 2002 2005 National Semiconductor Corporation ...

Page 2: ... Blank Page ...

Page 3: ...rd 7 5 1 Software Installation 7 5 2 Setting up the ADC08200 Evaluation Board 7 5 2 1 Board Set up 7 5 2 1 1 Computer Mode Operation 7 5 2 1 2 Manual Mode Operation 8 5 2 2 Quick Check of Analog Functions 8 5 2 3 Quick Check of Software and Computer Interface Operation 8 5 2 4 Getting Consistent Readings 8 5 2 5 Jumper Information 9 5 2 6 Troubleshooting 9 6 0 Evaluation Board Specifications 9 7 0...

Page 4: ... Blank Page 4 http www national com ...

Page 5: ...t and running WaveVision software operating under Microsoft Windows Use program WAVEVSN2 EXE available at National Semiconductor s web site 7 Connect a signal of 1 6VP P amplitude from a 50 Ohm source to Analog Input BNC J3 The ADC input signal can be observed at TP1 Because of isolation resistor R32 and the scope probe capacitance the input signal at TP1 will not have the same frequency response ...

Page 6: ...his 50 Ohm input is intended to accept a low noise sine wave signal of 1 6V peak to peak amplitude To accurately evaluate the ADC08200 dynamic performance the input test signal should be passed through a high quality bandpass filter 60dB minimum stop band attenuation as even the best signal sources do not provide a pure enough sine wave to properly evaluate an ADC The reference voltages for the AD...

Page 7: ...e ADC08200 is available at the 96 pin Euro connector J1 The series resistors of R35 isolate the ADC from the load circuit to reduce noise coupling into the ADC This evaluation package was designed to be easy and simple to use and to provide a quick and simple way to evaluate the ADC08200 The procedures given here will help you to properly set up the board 4 5 Power Supply Connections 5 2 1 Board S...

Page 8: ...rity and stability and that the sampling clock signal is extremely stable with minimal jitter 6 Adjust RV2 for a voltage of 0 27V to 0 33V at TP4 7 Adjust the signal source at Analog Input J3 for a signal amplitude of approximately 1 6VP P and check for the presence of that signal at TP1 This completes the testing of the analog portion of the evaluation board 5 2 3 Quick Check of Software and Comp...

Page 9: ...after turning on power before trying to capture data Be sure positions JP2 JP7 and JP8 are wired Be sure that the Digital Interface Board is connected to a serial printer port and has power Problem Opening Comm Port or Error Setting Comm State errors mean that the comm port selected is not the one to which the eval board is connected Be sure the proper port is selected type ALT O Ascertain that an...

Page 10: ... R33 not used C12 not used R34 0 R36 not used TP1 INPUT R32 100 C14 1uF R31 100 C11 10pF 1MEM JP6 DELAY1 C32 1uF 5V C34 1uF JP5 DELAY0 C13 1uF J1 96 Pin Female Q4 Q3 Q2 Q1 Q0 FF EF 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 D1 D0 PAF PAE GND REN1 RCLK REN2 OE RS WEN1 WCLK WEN2 LD VCC Q8 Q7 Q6 Q5 30 31 1 2 3 4 D8 D7 D6 D5 D4 D3 D2 Q4 Q3 Q2 Q1 Q0 FF EF 5 6 7 8 9 10 11 12 1...

Page 11: ...C10H125FN U2B MC10H125FN U2C MC10H125FN U2D MC10H125FN R22 47 R18 47 C6 1uF R27 510 5 2V C1 1uF R20 47 100MHz R21 47 _______ 100MHz T1 T4 6T 19 18 13 12 14 D CC __ CE VCC S Q _ Q R VEE 15 20 17 10 3 4 9 12 8 D CC __ CE VCC S Q _ Q R VEE 7 2 5 10 R14 47 OUT __ IN IN 8 9 7 R26 510 R17 47 JP1 ADCCLk Y1 200MHz 5 2V R11 330 C5 1uF OUT __ IN IN 3 4 5 2 20 R15 47 OUT __ IN IN 13 14 15 R13 330 R12 47 14 8...

Page 12: ...R52 100 Type 1206 26 2 R33A R33B 100 W Leaded 27 1 R53 130 Type 1206 28 1 R40 220 Type 1206 29 2 R10 R47 240 Type 1206 30 5 R1 R2 R11 R13 R46 330 Type 1206 31 5 R25 R26 R27 R28 R29 510 Type 1206 32 1 R4 1k Type 1206 33 1 R9 2 2k Type 1206 34 5 R24 R37 R39 R41 R44 4 7k Type 1206 35 1 R57 10k Type 1206 36 3 R30 R33 R36 not populated n a 37 1 R35 Resistor Pack 8 x 47 DigiKey 767 163 R47 ND 38 1 R49 R...

Page 13: ... Connect 1 2 Divide Clock Oscillator Y1 frequency by 2 Connect 2 3 Use Clock Oscillator Y1 frequency without dividing it Default JP2 Jumper Memory Connect 1 2 Use one FIFO chip Connect 2 3 Use both FIFO chips Default hard wired position JP3 thru JP6 Not Used JP7 Jumper Divide Enable Connect 1 2 Use both FIFO chips divide FIFO read signal frequency by 2 Default hard wired position Connect 2 3 Use o...

Page 14: ... D5 C18 ADC output D6 B19 ADC output D7 C19 ADC output D8 not used ADC output D9 not used ADC output D10 not used ADC output D11 not used GND A1 thru A24 A28 B28 C28 A31 B31 C31 Memory Read Clock B15 Reserved Signal B22 C22 C23 Reserved Power A25 A26 B25 B26 C25 C26 5V Logic Power Supply to Digital Interface Board Reserved Power 5 2V A29 B29 C29 Reserved Power 5V A32 B32 C32 14 http www national c...

Page 15: ... Blank Page 15 http www national com ...

Page 16: ...systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component in a life support device or system whose failure to perfor...

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