National Semiconductor ADC08200, Instruction Manual

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Y1
T1
U5
L4
+5V
GND
+5V
-5.2V
J4
POWER CONNECTOR
L2
L3
Q2
Q1
TP6
GND
NATIONAL SEMICONDUCTOR
ADC08200 EVAL BOARD
TP4
DGND
U9
U10
TP7
3VCC
U3
TP3
VRFB
TP1
INPUT
RV2
RV1
TP2
VTFT
U8
U2 U1
NUMEM
JP8
DIV_EN
JP7
TP5
DGND
U7
L1
J3
J3
JP2
MEM JP1
ADCCLK
JP5
DLY0
JP6
DLY1
J1
TP7
3VCC
J4
POWER
CONNECTOR
RV2
VTFB ADJ
RV1
VTFT ADJ
TP3
VTFB
J3
INPUT BNC
TP2
VTFT
TP7
INPUT
JP8
Detail:
Hard-Wired
Position
JP2, JP7
Detail:
Hard-Wired
Position
JP1
CLK FREQ
SELECT
JP1
Detail:
Default Jumper
Position
Figure 1. Component and Test Point Locations
4.0 Functional Description
4.2 ADC reference circuitry
The ADC08200 Evaluation Board schematic is shown in
Figure 2 .
The provided reference circuitry will provide nominal
reference voltage ranges of 1.3V to 2.5V for VRFT and
0V to 1.3V for VRFB, Providing for nominal input ranges
of 0V to 2.5V peak-to-peak.
4.1 Input (signal conditioning) circuitry
The input signal to be digitized should be applied to BNC
connector J3. This 50 Ohm input is intended to accept a
low-noise sine wave signal of 1.6V peak-to-peak
amplitude. To accurately evaluate the ADC08200
dynamic performance, the input test signal should be
passed through a high-quality bandpass filter (60dB
minimum stop-band attenuation) as even the best signal
sources do not provide a pure enough sine wave to
properly evaluate an ADC.
The reference voltages for the ADC08200 can be
monitored at test points TP2 and TP3 and are set with
RV1 and RV2. Signal offset can be provided by adjusting
both of these potentiometers.
4.3 ADC clock circuit
The board is shipped ready to accept an ECL clock
oscillator at a frequency of your choosing and is shipped
without an oscillator in its socket. 200 MHz oscillators are
not readily available, but a suitable 200 MHz oscillator is
available from Pletronics, Inc. as their part number
EC1145ME-200.0MPST.
The input to the ADC08200 is a.c. coupled through
capacitor C14. Resistors R33A and R33B provide the
needed input bias to the ADC08200. If d.c. coupling is
desired, be sure that the input signal remains within the
limits set by VRT at TP2 and VRB at TP3.
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