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JUMPER

FUNCTION

PINS 1 & 2

SHORTED

PINS 2 & 3

SHORTED

If  there  is  no  output  from  the  ADC08200,  perform  the
following:

JP1

Clock Select

Divide Clock

by 2

Do not Divide

Clock

Be  sure  that  the  proper  voltages  and  polarities  are
present  at  Power  Connector  P1  (especially  the
-5.2V).

JP2

No of Mem Chips

1 Mem Chip

2 Mem Chips

Be sure +3 Volts is present on terminals of L1, or at
TP7.

JP7

No of Mem Chips

2 Mem Chips

1 Mem Chip

Be  sure  that  R57  is  mounted  correctly.  See

http://www.national.com/appinfo/adc/files/ADC08200-R57.pdf

.

JP8

No of Mem Chips

1 Mem Chip

2 Mem Chips

Be sure there is an input  signal  at  J3  and  TP1  and
that  the  signal  source  and  input  filter  are  of
compatible frequencies.

Table 1.  Jumper settings.

5.2.6 Troubleshooting

Be sure positions JP2, JP7 and JP8 are wired.

"Comm Check Failed", "Error Transmitting", "Parallel Port
Time  Out  Error"  and/or  "Failed  to  communicate  with  the
board  on  LPT1"  errors  mean  communication  was
unsuccessful. Try the following:

If  the  displayed  waveform  appears  to  be  garbage,  or  if
the  FFT  plot  shows  nothing  but  noise  with  no  apparent
signal:

Be  sure  clock  Y1  is  of  the  proper  frequency
(200MHz) and type (ECL with output swing between
-0.6V and -1.3V).

Be  sure  to  wait  for  yellow  LED  D4  on  the  Digital
Interface  Board  to  go  out  after  turning  on  power
before trying to capture data.

Be sure positions JP2, JP7 and JP8 are wired.

Be sure that the Digital Interface Board is connected
to a serial printer port and has power.

Problem  Opening  Comm  Port"  or  "Error  Setting  Comm
State" errors mean that the comm port selected is not the
one to which the eval board is connected.

Be sure the proper port is selected (type 

ALT

-O).

Ascertain that an 80MHz clock oscillator is  properly
inserted into the socket at Y1 of the Digital Interface
Board  and  that  the  DIP  switches  on  the  Digital
Interface  Board  are  properly  set  (see  the  Digital
Interface  Board  manual).  Check  to  see  that  LEDs
D1 and D3 of the Digital Interface Board are on. See
the  Digital  Interface  Board  manual  for  their
functions.

Inconsistent  or  poor  performance  could  be  caused  by
reading the FIFO too fast. Reading fo the FIFO should be
done  at  10  MHz.  See  Digital  Interface  Board  manual  for
information  on  setting  the  sampling  frequency  of  that
board.

6.0 Evaluation Board Specifications

Be sure cable connections are solid.

Be  sure  that  the  board  to  computer  cable  is  not  a
Null  Modem  type.  If  it  is,  swap  the  jumpers  J8  and
J10 on the Digital Interface Board.

Board Size:

4.8" x 6.0" (12.2cm x 15.2 cm)

Power Requirements:

+ 5V ±5% @ 3.0 mA

     (see Section 4.6)

+ 5V ±5% @ 1 Amp
- 5.2V to -5.3V @ 250 mA

Clock Frequency Range:

10 MHz to 230 MHz

Analog Input

Nominal Voltage:

1.6VP-P

Frequency Range

50 KHz to 400 MHz

Impedance:

50 Ohms

9

          http://www.national.com

Summary of Contents for ADC08200

Page 1: ... Semiconductor December 2005 Rev 7 Evaluation Board Instruction Manual ADC08200 8 Bit 10 MSPS to 230 Msps Analog to Digital Converter with Internal Sample Hold 2001 2002 2005 National Semiconductor Corporation ...

Page 2: ... Blank Page ...

Page 3: ...rd 7 5 1 Software Installation 7 5 2 Setting up the ADC08200 Evaluation Board 7 5 2 1 Board Set up 7 5 2 1 1 Computer Mode Operation 7 5 2 1 2 Manual Mode Operation 8 5 2 2 Quick Check of Analog Functions 8 5 2 3 Quick Check of Software and Computer Interface Operation 8 5 2 4 Getting Consistent Readings 8 5 2 5 Jumper Information 9 5 2 6 Troubleshooting 9 6 0 Evaluation Board Specifications 9 7 0...

Page 4: ... Blank Page 4 http www national com ...

Page 5: ...t and running WaveVision software operating under Microsoft Windows Use program WAVEVSN2 EXE available at National Semiconductor s web site 7 Connect a signal of 1 6VP P amplitude from a 50 Ohm source to Analog Input BNC J3 The ADC input signal can be observed at TP1 Because of isolation resistor R32 and the scope probe capacitance the input signal at TP1 will not have the same frequency response ...

Page 6: ...his 50 Ohm input is intended to accept a low noise sine wave signal of 1 6V peak to peak amplitude To accurately evaluate the ADC08200 dynamic performance the input test signal should be passed through a high quality bandpass filter 60dB minimum stop band attenuation as even the best signal sources do not provide a pure enough sine wave to properly evaluate an ADC The reference voltages for the AD...

Page 7: ...e ADC08200 is available at the 96 pin Euro connector J1 The series resistors of R35 isolate the ADC from the load circuit to reduce noise coupling into the ADC This evaluation package was designed to be easy and simple to use and to provide a quick and simple way to evaluate the ADC08200 The procedures given here will help you to properly set up the board 4 5 Power Supply Connections 5 2 1 Board S...

Page 8: ...rity and stability and that the sampling clock signal is extremely stable with minimal jitter 6 Adjust RV2 for a voltage of 0 27V to 0 33V at TP4 7 Adjust the signal source at Analog Input J3 for a signal amplitude of approximately 1 6VP P and check for the presence of that signal at TP1 This completes the testing of the analog portion of the evaluation board 5 2 3 Quick Check of Software and Comp...

Page 9: ...after turning on power before trying to capture data Be sure positions JP2 JP7 and JP8 are wired Be sure that the Digital Interface Board is connected to a serial printer port and has power Problem Opening Comm Port or Error Setting Comm State errors mean that the comm port selected is not the one to which the eval board is connected Be sure the proper port is selected type ALT O Ascertain that an...

Page 10: ... R33 not used C12 not used R34 0 R36 not used TP1 INPUT R32 100 C14 1uF R31 100 C11 10pF 1MEM JP6 DELAY1 C32 1uF 5V C34 1uF JP5 DELAY0 C13 1uF J1 96 Pin Female Q4 Q3 Q2 Q1 Q0 FF EF 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 D1 D0 PAF PAE GND REN1 RCLK REN2 OE RS WEN1 WCLK WEN2 LD VCC Q8 Q7 Q6 Q5 30 31 1 2 3 4 D8 D7 D6 D5 D4 D3 D2 Q4 Q3 Q2 Q1 Q0 FF EF 5 6 7 8 9 10 11 12 1...

Page 11: ...C10H125FN U2B MC10H125FN U2C MC10H125FN U2D MC10H125FN R22 47 R18 47 C6 1uF R27 510 5 2V C1 1uF R20 47 100MHz R21 47 _______ 100MHz T1 T4 6T 19 18 13 12 14 D CC __ CE VCC S Q _ Q R VEE 15 20 17 10 3 4 9 12 8 D CC __ CE VCC S Q _ Q R VEE 7 2 5 10 R14 47 OUT __ IN IN 8 9 7 R26 510 R17 47 JP1 ADCCLk Y1 200MHz 5 2V R11 330 C5 1uF OUT __ IN IN 3 4 5 2 20 R15 47 OUT __ IN IN 13 14 15 R13 330 R12 47 14 8...

Page 12: ...R52 100 Type 1206 26 2 R33A R33B 100 W Leaded 27 1 R53 130 Type 1206 28 1 R40 220 Type 1206 29 2 R10 R47 240 Type 1206 30 5 R1 R2 R11 R13 R46 330 Type 1206 31 5 R25 R26 R27 R28 R29 510 Type 1206 32 1 R4 1k Type 1206 33 1 R9 2 2k Type 1206 34 5 R24 R37 R39 R41 R44 4 7k Type 1206 35 1 R57 10k Type 1206 36 3 R30 R33 R36 not populated n a 37 1 R35 Resistor Pack 8 x 47 DigiKey 767 163 R47 ND 38 1 R49 R...

Page 13: ... Connect 1 2 Divide Clock Oscillator Y1 frequency by 2 Connect 2 3 Use Clock Oscillator Y1 frequency without dividing it Default JP2 Jumper Memory Connect 1 2 Use one FIFO chip Connect 2 3 Use both FIFO chips Default hard wired position JP3 thru JP6 Not Used JP7 Jumper Divide Enable Connect 1 2 Use both FIFO chips divide FIFO read signal frequency by 2 Default hard wired position Connect 2 3 Use o...

Page 14: ... D5 C18 ADC output D6 B19 ADC output D7 C19 ADC output D8 not used ADC output D9 not used ADC output D10 not used ADC output D11 not used GND A1 thru A24 A28 B28 C28 A31 B31 C31 Memory Read Clock B15 Reserved Signal B22 C22 C23 Reserved Power A25 A26 B25 B26 C25 C26 5V Logic Power Supply to Digital Interface Board Reserved Power 5 2V A29 B29 C29 Reserved Power 5V A32 B32 C32 14 http www national c...

Page 15: ... Blank Page 15 http www national com ...

Page 16: ...systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component in a life support device or system whose failure to perfor...

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