National Instruments NI-6589, Getting Started Manual

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CLIP Name Signals Description
■
One LVDS clock output
signal
■
Four single-ended PFI
lines
■
One single-ended
clock input signal
Boolean control. In the U8 data type, the top four
bits are unused. Each LVDS line, PFI line, and clock
output is connected to an OSERDES or ISERDES
block that serializes or deserializes, respectively,
the signal by a factor of six by default. Therefore,
with every regional clock cycle, the NI 6589 reads or
writes six samples to or from the ISERDES or
OSERDES blocks. All OSERDES and ISERDES blocks
are set to double data rate (DDR) mode.
Table 4. NI 6589 CLIP Items
The following table lists the NI 6589 SMA connector signals and corresponding
FlexRIO FPGA module signals necessary for designing custom component-level IP
(CLIP).
NI 6589 FlexRIO FPGA Module
Signal Name GPIO Input GPIO Output GPIO Direction
PFI 0 GPIO_2_n GPIO_5_n GPIO_6_n (as enable)
CLOCK IN GClk_SE — —
Table 5. NI 6589 SMA Signals and FlexRIO FPGA Module Signals
The following table lists the NI 6589 DDC connector signals and corresponding
FlexRIO FPGA module signals necessary for designing custom component-level IP
(CLIP). The _CC suffix on signals identifies channels that can receive a regional
clock.
NI 6589 FlexRIO FPGA Module
Signal Name GPIO Input GPIO Output GPIO Direction
PFI 1+ GPIO_39_CC GPIO_36 GPIO_14
PFI 1- GPIO_39_n_CC GPIO_36_n
PFI 2+ GPIO_40_CC GPIO_41 GPIO_14_n
PFI 2- GPIO_40_n_CC GPIO_41_n
PFI 3+ GPIO_45 GPIO_46 GPIO_15
PFI 3- GPIO_45 _n GPIO_46_n
PFI 4+ GPIO_47 GPIO_48 GPIO_15_n
PFI 4- GPIO_47_n GPIO_48_n
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