National Instruments NI-6589, Getting Started Manual

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Figure 8. Crosspoint Switch
Sync Clock (PXIe Only)
Adapter Module Onboard Clock
STROBE
Reserved
Strobe Bypass Control
from NI FlexRIO FPGA Module
(GPIO_8_n)
2
2 2
2
2
Generation Bank I/O Clock
to NI FlexRIO FPGA Module
GPIO_26_CC
GPIO_26_n_CC
2
PFI Bank I/O Clock
to NI FlexRIO FPGA Module
GPIO_38_CC
GPIO_38_n_CC
2
Global Clock
to NI FlexRIO FPGA Module
UserGclkLvds
UserGclkLvds_n
Acquisition Bank I/O Clock
to NI FlexRIO FPGA Module
GPIO_56_CC
GPIO_56_n_CC
2
2
2
4×4
Crosspoint
Switch
2
Related concepts
■
Component-Level Intellectual Property (CLIP)
Component-Level Intellectual Property (CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for
HDL IP integration. FlexRIO devices support two types of CLIP: user-defined and
socketed.
■
User-defined CLIP allows you to insert HDL IP into an FPGA target, enabling
VHDL code to communicate directly with an FPGA VI.
■
Socketed CLIP provides the same IP integration of the user-defined CLIP,
but it also allows the CLIP to communicate directly with circuitry external to
the FPGA. Adapter module socketed CLIP allows your IP to communicate
directly with both the FPGA VI and the external adapter module connector
interface.
The FlexRIO adapter module ships with socketed CLIP items that add module I/O to
the LabVIEW project.
Related reference
■
Block Diagrams
© National Instruments
15
NI-6589