National Instruments NI-6589, Getting Started Manual

Page: 20 / 22

Gen_IO_Clock_Source, PFI_IO_Clock_Source, and
IO_Module_Clock_1_Source cannot be set to Strobe From Crosspoint
Switch.
Figure 9. Crosspoint Switch
Sync Clock (PXIe Only)
Adapter Module Onboard Clock
STROBE
Reserved
Strobe Bypass Control
from NI FlexRIO FPGA Module
(GPIO_8_n)
2
2 2
2
2
Generation Bank I/O Clock
to NI FlexRIO FPGA Module
GPIO_26_CC
GPIO_26_n_CC
2
PFI Bank I/O Clock
to NI FlexRIO FPGA Module
GPIO_38_CC
GPIO_38_n_CC
2
Global Clock
to NI FlexRIO FPGA Module
UserGclkLvds
UserGclkLvds_n
Acquisition Bank I/O Clock
to NI FlexRIO FPGA Module
GPIO_56_CC
GPIO_56_n_CC
2
2
2
4×4
Crosspoint
Switch
2
In software, each clock output terminal is accessed with a U8 data type. The
following table shows the values of the crosspoint switch clock options.
Value Clock Option
0
Tristate
—Output disabled (high impedance).
2
Sync Clock (PXI Express Only)
—Clock from PXI Express backplane. You can select
PXI_CLK10
or
DStarA
in the
Details
category of the
IO Module Properties
dialog box.
3
Adapter Module Onboard Clock
—Clock generated from the Si570 clock chip.
4
Strobe From Crosspoint Switch
—LVDS STROBE signal from crosspoint switch. Use this
setting to route the LVDS STROBE signal to multiple I/O clocks.
5
Strobe Bypass
—LVDS STROBE bypasses the crosspoint switch. The propagation delay of
the
Strobe Bypass
exactly matches the propagation delay of the data channels. This
setting is ideal for source- synchronous applications.
Table 7. Clock Values
Where to Go Next
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