NI 6589
FlexRIO FPGA Module
Signal Name
GPIO Input
GPIO Output
GPIO Direction
DIO 15+
GPIO_59_CC
GPIO_16
GPIO_1_n
DIO 15-
GPIO_59_n_CC
GPIO_16_n
GPIO_56_CC
—
GPIO_8_n
GPIO_26_CC
GPIO_38_CC
GPIO_LVDS
STROBE-
GPIO_56_n_CC
GPIO_26_n_CC
GPIO_38_CC
GPIO_LVDS_n
DDC CLOCK OUT LVDS+
—
GPIO_43
GPIO_7_n (as enable)
DDC CLOCK OUT LVDS-
GPIO_43_n
SE_PFI_1
GPIO_44_n
GPIO_37_n
GPIO_44 (as enable)
SE_PFI_2
GPIO_42_n
GPIO_34_n
GPIO_42 (as enable)
SE_PFI_3
GPIO_35
GPIO_33_n
GPIO_35_n (as enable)
Table 6. NI 6589 DDC Signals and FlexRIO FPGA Module Signals
Refer to the FlexRIO Help for more information about FlexRIO CLIP items,
configuring the NI 6589 with a socketed CLIP, and a list of available socketed CLIP
signals.
Clocking
The clocks on the NI 6589 control the sample rate and other timing functions on
your FlexRIO system. The following figure shows the NI 6589 clock sources routed
through the crosspoint switch. The Generation Bank I/O clock, PFI Bank I/O clock,
and Global clock are all sourced by the crosspoint switch. The Acquisition Bank I/O
clock can be sourced from the crosspoint switch or accessed directly through the
Strobe Bypass path.
Note
Only the Acq_IO_Clock_Source signal can use the STROBE Bypass
path. If Acq_IO_Clock_Source is set to Strobe Bypass, then
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NI-6589
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