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Chapter 3

Register Map and Descriptions — Channel B Mode Register

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National Instruments Corporation

3-23

AT-MIO E Series RLPM

Channel B Mode Register

The Channel B Mode Register contains 8 bits that control the logical DMA channel B. The
contents of this register are cleared upon power up and after a reset condition.

Address:

Base a 05 (hex)

Type:

Write-only

Word Size:

8-bit

Bit Map:

Bit

Name

Description

7

ChanEnable

DMA Channel B Enable—This bit enables DMA channel
B to process DMA request/acknowledge cycles. If this bit
is set, any requests on channel B are translated to the
physical DMA interface. If this bit is cleared, any logical
requests are ignored. All other setup for logical channel B
should be performed prior to setting this bit. This bit must
be cleared between acquisition sequences to properly
initialize the circuitry.

6

TCIntEnable

DMATCB Interrupt Enable—This bit enables an interrupt
to be generated whenever a DMATCB occurs. The
interrupts are enabled when this bit is set and disabled
when cleared.

5–3

Transfer<2..0>

Transfer Type 2 through 0—These three bits determine the
size and type of the DMA transfer. If Transfer<2..0> is set
to 0, DMA requests are generated for single transfers. If
Transfer<2..0> is set to 1, the DMA request is asserted for
up to eight transfers without rearbitration.

2–0

Channel<2..0>

Physical Channel Select 2 through 0—These three bits
select which physical channel is associated with logical
channel B. The AT E Series can use only 16-bit DMA
channels, so these bits must be set appropriately.

7

6

5

4

3

2

1

0

ChanEnable

TCIntEnable

Transfer2

Transfer1

Transfer0

Channel2

Channel1

Channel0

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Summary of Contents for AT-AI-16XE-10

Page 1: ...DAQ AT MIO E Series Register Level Programmer Manual Multifunction I O Boards for the PC AT AT MIO E Series RLPM August 1998 Edition Part Number 340747C 01...

Page 2: ...36 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 6120092 Italy 02 413091 Ja...

Page 3: ...of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments sh...

Page 4: ...og Input Circuitry 2 8 Data Acquisition Timing Circuitry 2 11 Single Read Timing 2 11 Data Acquisition Sequence Timing 2 12 Posttrigger and Pretrigger Acquisition 2 18 Analog Triggering 2 19 Analog Ou...

Page 5: ...Strobes Register 3 21 Channel A Mode Register 3 22 Channel B Mode Register 3 23 Channel C Mode Register 3 24 AI AO Select Register 3 25 G0 G1 Select Register 3 26 DIO Register Group 3 26 DAQ STC Regi...

Page 6: ...nes Programming Considerations 4 48 Analog Triggering 4 49 Interrupt Programming 4 52 DMA Programming 4 53 Single Channel Versus Dual Channel DMA 4 54 Chapter 5 Calibration EEPROM 5 1 Calibration DACs...

Page 7: ...Figure 2 17 Analog Output Circuitry Block Diagram 2 20 Figure 2 18 DAQ STC Counter Diagram 2 24 Figure 2 19 RTSI Bus Interface Circuitry Block Diagram 2 25 Figure 4 1 Analog Trigger Structure 4 50 Fi...

Page 8: ...nderstanding of AT E Series board programming Unless otherwise noted text applies to all boards in the AT E Series The AT E Series boards are AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 AT MI...

Page 9: ...u communicate with National Instruments about our products The Glossary contains an alphabetical list and description of terms used in this manual including acronyms abbreviations metric prefixes mnem...

Page 10: ...cuments helpful for programming interrupts and DMA Programming Interrupts for Data Acquisition on 80x86 Based Computers Application Note 010 Programming DMA on PC XT AT Computers Application Note 029...

Page 11: ...e chip to connect the board to the AT I O bus The DAQ PnP implements the Plug and Play ISA Specification so that the DMA interrupts and base I O addresses are all software configurable This allows you...

Page 12: ...analog and digital triggering AT MIO 16E 2 16 single ended or eight differential 12 bit analog inputs 500 kS s two 12 bit analog outputs eight digital I O analog and digital triggering AT MIO 64E 3 6...

Page 13: ...O 8 12 Bit Sampling A D Converter EEPROM Configuration Memory NI PGIA Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs Dither Circuitry Trigger Anal...

Page 14: ...itches Analog Muxes Voltage REF Calibration DACs Dither Circuitry 6 Calibration DACs DAC0 DAC1 3 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O...

Page 15: ...tion Switches Analog Muxes Voltage REF Calibration DACs 4 Calibration DACs DAC0 DAC1 7 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus...

Page 16: ...ation Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs 7 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Inter...

Page 17: ...utput operations The timing I O circuitry information in this manual is skeletal in nature and is sufficient in most Timing PFI Trigger I O Connector 3 2 RTSI Bus AT I O Channel Digital I O 8 16 Bit S...

Page 18: ...bus a DMA arbitration bus interrupt lines and several control and support signals Figure 2 6 shows the functional blocks making up the AT E Series ISA bus interface circuitry Figure 2 6 ISA Bus Inter...

Page 19: ...particular read or write cycle These accesses are controlled by the base address decoding SA 4 0 and the ISA control lines when the CPU is trying to access the board In the case of DMA transfers the...

Page 20: ...og input operation Figure 2 7 shows a general block diagram for the analog input circuitry Figure 2 7 Analog Input and Data Acquisition Circuitry Block Diagram Analog Input Circuitry The general model...

Page 21: ...dicates which channel of the specified type will be used during the conversion while the bank field indicates which bank of 16 channels is active This bank field is used on boards that have more than...

Page 22: ...These modes correspond to ranges of 32 768 to 32 767 in bipolar mode and 0 to 65 535 in unipolar mode The AT E Series boards include a 16 bit wide FIFO to buffer the analog input data This buffering w...

Page 23: ...explained in the DAQ STC Technical Reference Manual If you have not read the functional description of each DAQ STC module you must do so before completing this register level programmer manual Singl...

Page 24: ...eration The SI2 counter is a 16 bit counter in the DAQ STC This counter determines the interval between CONVERT pulses It can be programmed for a maximum interval of 3 3 ms and a minimum interval of 5...

Page 25: ...rogram your configuration memory as follows 1 channel 0 gain 50 2 channel 5 gain 2 3 channel 3 gain 10 last channel You should program SI2 for 10 s SI for 100 s and SC for 50 50 scans Figure 2 9 shows...

Page 26: ...isition Notice that channel 0 is sampled once every 100 s Hence its sampling rate is 10 kS s whereas channel 1 is sampled once every 200 s Its rate is 5 kS s Similarly you could implement any 1 x rati...

Page 27: ...mpling Rate Here channel 0 is sampled three times whereas channels 1 and 2 are sampled once every three scans Figure 2 13 Multirate Scanning of Three Channels with 4 2 1 Sampling Rate 0 0 0 0 0 0 1 ST...

Page 28: ...gures 2 14 and 2 16 illustrate the advantages of using the ghost feature Figure 2 12 shows example 3 timing and Figure 2 16 shows the same example using ghost Example 3 channel 1 channel 0 2 3 without...

Page 29: ...indicate channel 1 samples that are actually stored in the FIFOs Table 2 1 shows what the configuration memory would look like The symbol indicates that ghost or last channel is absent Now both channe...

Page 30: ...etrigger count and the posttrigger count To begin with the pretrigger count is loaded into the SC Acquisition is then started through either software by strobing a bit or through hardware by externall...

Page 31: ...erial DAC that sets each of the high and low thresholds These thresholds are within full scale The selected input is compared against each of these thresholds by a comparator The outputs of the compar...

Page 32: ...one of these features The AT AI 16XE 10 does not have analog output Each analog output channel contains a 12 bit DAC an amplification stage and an onboard voltage reference except for the and AT MIO...

Page 33: ...corresponding to an LSB change in the digital code word For unipolar output 1 LSB Vref 4 096 For bipolar output 1 LSB Vref 2 048 For 16 bit DAC 1 LSB Vref 8 192 in unipolar mode and 1 LSB Vref 4 096...

Page 34: ...irectly to the DACs under software control without the use of the timing engine provided in the DAQ STC This is typically useful for setting the analog outputs to DC levels where precise timing of the...

Page 35: ...fer the data instead it will transfer it directly to the first buffer of the destination DAC After the data has been transferred the DAQ PnP will set the FIFO full flag indicating that no more data is...

Page 36: ...abled and generates timing signals at its OUT output pin The UPDOWN pin determines the direction of counting Active polarities of these pins are software selectable in the DAQ STC Notice that on the A...

Page 37: ...19 shows a block diagram of the RTSI bus interface circuitry Figure 2 19 RTSI Bus Interface Circuitry Block Diagram The RTSI functionality is provided in the DAQ STC chip This RTSI Trigger Module con...

Page 38: ...by eight internally generated timing signals and the four RTSI Board signals Similarly the four RTSI Board signals can be driven by any of the RTSI Trigger bus signals Of the four RTSI board signals o...

Page 39: ...et to the I O base address of the AT E Series board Registers are grouped in the table by function Each register group is introduced in the order shown in Table 3 1 then described in detail including...

Page 40: ...gister Configuration Memory Low Configuration Memory High 1C 10 12 28 16 18 Read only Write only Write only 16 bit 16 bit 16 bit Analog Output Register Group AO Configuration DAC FIFO Data DAC0 Direct...

Page 41: ...tatus 2 AO Status 2 DIO Parallel Input 0 2 4 6 8 A C E 4 6 8 A C E 0 2 4 6 8 10 12 14 4 6 8 10 12 14 Read and write Read and write Write Write Write Write Write Write Write Read Read Read Read Read Re...

Page 42: ...1 Each register group is introduced followed by a detailed bit description The individual register description gives the address type word size and bit map of the register followed by a description of...

Page 43: ...hird set of serial DACs with the serial data previously shifted into the DACs AT MIO 16XE 10 and AT AI 16XE 10 only 4 SerDacLd1 Serial DAC Load1 This bit is used to load the second set of serial DACs...

Page 44: ...n the low to high transition of the serial clock Misc Command Register The Misc Command Register contains one bit that controls the AT E Series analog trigger source The contents of this register are...

Page 45: ...ATCC will be set This bit is cleared by the DmaTcCClr bit in the Strobes Register 2 DMATCB DMA Terminal Count B This bit indicates the status of the DMA process on the selected DMA Channel B When all...

Page 46: ...r another ADC conversion value to be stored Values are shifted into the ADC FIFO whenever an ADC conversion is complete unless the GHOST bit is set in that entry of the Configuration Memory The ADC FI...

Page 47: ...urn values ranging from 0 to 4 095 decimal 0x0000 to 0x0FFF when the ADC is in unipolar mode and 2 048 to 2 047 decimal 0xF800 to 0x07FF when the ADC is in bipolar mode The boards with a 16 bit ADC wi...

Page 48: ...astChan Last Channel This bit should be set in the last entry of the scan sequence loaded into the channel configuration memory More than one occurrence of the LastChan bit is possible in the configur...

Page 49: ...t configures the ADC for unipolar or bipolar mode When Unip Bip is set the ADC is configured for unipolar operation and values read from the ADC Data Register are in straight binary format When Unip B...

Page 50: ...control register in the DAQ STC Address Base address 12 hex Type Write only Word Size 16 bit Bit Map Bit Name Description 15 11 6 Reserved Reserved Always write 0 to these bits 14 12 ChanType 2 0 Cha...

Page 51: ...ne bank for CAL 3 0 Chan 3 0 Channel Select 3 through 0 These bits indicate which channel is active for the current resource in the scan list Not every resource uses all 16 channels in a bank Channel...

Page 52: ...1 ACh9 0010 ACh2 ACh10 0011 ACh3 ACh11 0100 ACh4 ACh12 0001 ACh5 ACh13 0110 ACh6 ACh14 0111 ACh7 ACh15 1xxx Reserved Reserved Table 3 6 Nonreferenced Single Ended Channel Assignments Type 2 0 NRSE Cha...

Page 53: ...ments Type 2 0 RSE Chan 3 0 PGIA PGIA 0000 ACh0 AIGround 0001 ACh1 AIGround 0010 ACh2 AIGround 0011 ACh3 AIGround 0100 ACh4 AIGround 0101 ACh5 AIGround 0110 ACh6 AIGround 0111 ACh7 AIGround 1000 ACh8...

Page 54: ...output configuration The contents of this register are cleared upon power up and after a reset condition Address Base address 16 hex Type Write only Word Size 16 bit Bit Map Bit Name Description 15 9...

Page 55: ...nal 10 Vref is used for the DAC reference This bit is reserved on the AT MIO 16XE 50 AT MIO 16XE 10 and AT AI 16XE 10 It should be set to 0 1 ReGlitch Reglitch DAC When set this bit configures the sel...

Page 56: ...is free to write additional data Address Base address 1E hex Type Write only Word Size 16 bit Bit Map Bit Name Description 15 12 D 15 12 Reserved Always write 0 to these bits except AT MIO 16XE 10 an...

Page 57: ...12 bit data to be written to DAC data FIFO This data is interpreted in straight binary form when DAC0 is configured for unipolar operation When DAC0 is configured for bipolar operation the data is int...

Page 58: ...it data to be written to the DAC data FIFO This data is interpreted in straight binary form when DAC1 is configured for unipolar operation When DAC1 is configured for bipolar operation the data is int...

Page 59: ...6 bit DMA channels available on the EISA bus Strobes Register The Strobes Register contains 3 bits that clear the DMA terminal count status bits These bits are cleared by hardware after each write The...

Page 60: ...d prior to setting this bit This bit must be cleared between acquisition sequences to properly initialize the circuitry 6 TCIntEnable DMATCA Interrupt Enable This bit enables an interrupt to be genera...

Page 61: ...d prior to setting this bit This bit must be cleared between acquisition sequences to properly initialize the circuitry 6 TCIntEnable DMATCB Interrupt Enable This bit enables an interrupt to be genera...

Page 62: ...d prior to setting this bit This bit must be cleared between acquisition sequences to properly initialize the circuitry 6 TCIntEnable DMATCC Interrupt Enable This bit enables an interrupt to be genera...

Page 63: ...annels to be used by the analog output This resource supports both single and dual channel DMA therefore either one or two of the three bits must be set for proper operation These bits must be set pri...

Page 64: ...first channel to transfer data is the first alphabetically These bits must be set prior to enabling the logical channels 2 0 GPCT0 C A General Purpose Counter Timer 0 Logical Channel C through A These...

Page 65: ...iguration Memory Clear Register Accessing the Configuration Memory Clear Register clears all information in the channel configuration memory and resets the write pointer to the first location in the m...

Page 66: ...in the DAQ STC Technical Reference Manual These operations are explained in terms of bitfields A bitfield is defined as a group of contiguous bits that jointly perform a function Using bitfields has...

Page 67: ...on of the full Plug and Play protocol is beyond the scope of this manual and is discussed in the ISA Plug and Play Specification version 1 0 available from Intel This section discusses how to assign a...

Page 68: ...tion state The base I O address for the board can now be assigned The E Series boards use full 16 bit decoding so both the high and low bytes of the base I O address must be assigned This assignment i...

Page 69: ...the address offset to the Window_Address_ Register read from the Window_Data_Read_Register Programming Examples The programs presented in this chapter are broken into five sections Digital I O Analog...

Page 70: ...copies of the registers If you wish to write your own examples or modify these examples we strongly recommend adding software copies of the write only registers Please refer to Chapter 2 Register and...

Page 71: ...d 7 as inputs DIO_Control_Register 0x55 3 Write the digital pattern DIO_Output_Register 0x00 4 Read the digital pattern Pattern DIO_Parallel_Input Register 5 Repeat Steps 3 and 4 for subsequent patter...

Page 72: ...le 1 This manual provides the structure and pseudo code for each example The AT E Series Register Level Programmer Manual Companion Disk contains the complete programs The following pseudo code exampl...

Page 73: ...ion_Memory_Low_Register Last channel 1 Gain 1 Polarity 0 Dither enable 0 3 The programming of the DAQ STC begins with the clock configuration The function MSC_Clock_Configure selects the timebase for...

Page 74: ...I configuration end 1 7 Call the function AI_Initialize_Configuration_Memory_ Output to output one pulse and access the first value in the configuration FIFO AI_Command_1_Register Convert pulse 1 8 Th...

Page 75: ...tion start 1 AI_Start_Stop_Select_Register Stop select 19 Stop sync 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 12 Same as Step 4 13 Now start the acquisition with AI_Start_...

Page 76: ...onfiguration start 1 AI_SC_Load_A_Registers 24 bits Number of posttrigger scans 1 4 AI_Command_1_Register AI SC Load 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 5 The functi...

Page 77: ...egister AI SC arm 1 AI SI arm 1 AI SI2 arm 1 AI DIV arm 1 10 The function AI_Start_The_Acquisition starts the acquisition process AI_Command_2_Register AI START1 Pulse 1 11 Poll the AI FIFO not empty...

Page 78: ...u are using 2 Use the getvect and setvect functions to replace the default interrupt handler with your ISR You should disable interrupts during this step 3 Reset the interrupt controller hardware 4 Pe...

Page 79: ...vert signal for the acquisition Joint_Reset_Register AI configuration start 1 AI_SI2_Load_A_Register AI SI2 special ticks 1 1999 AI_SI2_Load_B_Register AI SI2 ordinary ticks 1 1999 AI_Mode_2_Register...

Page 80: ...vice_Routine while 20 samples have not been read Example 4 Example 4 performs the same acquisition as Example 2 but with DMA Acquire 5 scans at a scan interval of 1ms The scan list contains channels 5...

Page 81: ...ync 1 AI_SI_Load_A_Registers 24 bits AI SI special ticks 1 1 AI_Command_1_Register AI SI load 1 AI_SI_Load_A_Registers 24 bits AI SI ordinary ticks 1 19999 Joint_Reset_Register AI configuration start...

Page 82: ...A_Mode_Register DMA A channel enable 1 Interrupt_B_Enable_Register MSC pass thru interrupt enable 1 10 The function AI_Interrupt_Enable enables interrupts for the acquisition Interrupt_A_Enable_Regist...

Page 83: ...onnected to PFI1 to trigger each scan Use polled input to read the AI FIFO data 1 Perform Analog Input Example 1 Step 1 2 Perform Analog Input Example 1 Step 2 for each channel in the scan list Only c...

Page 84: ...t signal for the acquisition Joint_Reset_Register AI configuration start 1 AI_Mode_3_Register AI SI2 source 1 AI_SI2_Load_A_Register AI SI2 special ticks 1 1999 AI_SI2_Load_B_Register AI SI2 ordinary...

Page 85: ...te to 100 s Connect the stop trigger to PFI1 Acquire 10 scans after the stop trigger leaving 10 scans before the stop trigger Use polled input to read the AI FIFO data 1 Perform Analog Input Example 1...

Page 86: ...T_STOP_Select_Register 0x0060 AI_SI_Load_A_Registers 24 bits AI SI special ticks 1 1 AI_Command_1_Register AI SI load 1 AI_SI_Load_A_Registers 24 bits AI SI ordinary ticks 1 19999 Joint_Reset_Register...

Page 87: ...s_1_Register is not set or the AIFIFO not empty Example 7 Example 7 performs the same scanning as Example 2 but as a single wire acquisition Acquire 5 scans The scan list contains channels 5 4 1 and 0...

Page 88: ...11 7 Convert_Signal selects the convert signal for the acquisition Joint_Reset_Register AI configuration start 1 AI_Mode_2_Register AI SC gate enable 1 AI START STOP gate enable 1 AI_Mode_1_Register...

Page 89: ...pare the unscaled results to the applied voltage Read the samples using polled input 1 Perform Analog Input Example 1 Step 1 2 Perform Analog Input Example 1 Step 2 for channel 3 3 Perform Analog Inpu...

Page 90: ...egisters 24 bits AI AI ordinary ticks 1 199 Joint_Reset_Register AI configuration start 0 AI configuration end 1 8 Perform Analog Input Example 1 Step 11 9 Convert_Signal selects the convert signal fo...

Page 91: ...wer single board configuration no temperature setting and the shield unconnected Scan channels 0 through 7 on the AMUX 64T Acquire 10 scans at a scan interval of 200 s and a sample interval of 20 s Co...

Page 92: ...ect 3 AI_DIV_Load_A_Register AI number of channels ratio 1 3 AI_Command_1_Register AI DIV load 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 6 Perform Analog Input Example 1 S...

Page 93: ...nfiguration start 1 AI_SI2_Load_A_Register AI SI2 special ticks 1 399 AI_SI2_Load_B_Register AI SI2 ordinary ticks 1 399 AI_Mode_2_Register AI SI2 reload mode 1 AI_Command_1_Register AI SI2 load 1 AI_...

Page 94: ...the DAQ STC Analog output DAQ STC programming consists of the following functions AO_Reset_All MSC_Clock_Configure AO_Board_Personalize AO_Triggering AO_Counting AO_Updating AO_Channels AO_LDAC_Source...

Page 95: ..._Configuration_Register DACSel 3 0 1 BipDac 1 ExtRef 0 ReGlitch 0 GroundRef 0 3 Call AO_Reset_All to reset the DAQ STC Joint_Reset_Register AO configuration start 1 AO_Command_1_Register AO disarm 1 I...

Page 96: ...er results in 5V appearing at the OUT1 line Example 2 This example generates a waveform using polled writes to the data FIFO Initialize the buffer with 3000 points Use polled writes to write each poin...

Page 97: ...Register AO BC source select 1 Interrupt_B_Ack_Register 0x3F98 Joint_Reset_Register AO configuration start 0 AO configuration end 1 8 Call AO_Board_Personalize to configure the DAQ STC for the MIO boa...

Page 98: ...the first buffer contains 3000 points Write 2999 to UC Load Register A each subsequent buffer contains 3000 points Joint_Reset_Register AO configuration start 1 AO_Mode_1_Register AO continuous 0 AO_...

Page 99: ...initial load source 0 AO UI reload mode 0 AO_UI_Load_A_Registers 24 bits AO UI special ticks 1 1 AO_Command_1_Register AO UI load 1 AO_UI_Load_A_Registers 24 bits AO UI ordinary ticks 1 9C40 Joint_Res...

Page 100: ...Joint_Reset_Register AO configuration start 0 AO configuration end 1 15 Call AO_FIFO to disable the FIFO retransmit Joint_Reset_Register AO configuration start 1 AO_Mode_2_Register AO FIFO retransmit...

Page 101: ...IO 16XE 50 Initialize the data FIFO with a 100 point buffer Output the buffer 50 times The update interval is 100 microseconds Confirm operation with an oscilloscope 1 Perform Analog Output Example 2...

Page 102: ...Load the UI counter with 1 minimum delay from the START1 to the first UPDATE Write 1999 to UI Load Register A 100 microsecond update interval Joint_Reset_Register AO configuration start 1 AO_Command_...

Page 103: ..._Acquisition to pulse the software START1 trigger AO_Command_2_Register AO START1 pulse 1 Example 4 This example generates a waveform using local buffer mode with external UPDATE and external trigger...

Page 104: ...r with 49 output the buffer 50 times Load the UC counter with 100 the first buffer contains 100 points Write 99 to UC Load Register A each subsequent buffer contains 100 points Joint_Reset_Register AO...

Page 105: ...AQ STC When the status register indicates an interrupt the main loop transfers control to the ISR To use the example ISR as an actual interrupt you need to learn how to install software interrupts on...

Page 106: ...ter 0x554 5 Program the DAQ STC to generate interrupts on the FIFO condition Interrupt_B_Enable_Register AO FIFO interrupt enable 1 Interrupt_Control_Register Interrupt B output select IRQ number Inte...

Page 107: ...n the general purpose counter and timer module of DAQ STC with specific programming steps in the programming information section Example 1 illustrates simple gated event counting Example 2 shows buffe...

Page 108: ...value G0_Command_Register G0_Load 1 G0_Input_Select_Register G0_Source_Select 4 PFI3 G0_Source_Polarity 0 rising edges G0_Gate_Select 5 PFI4 G0_OR_Gate 0 G0_Output_Polarity 0 active high G0_Gate_Selec...

Page 109: ...The counter uses G_In_TimeBase as G_Source to measure the signal s pulse width on PFI4 G_Gate counting the number of the edges that occur on G_Source At the completion of each pulse width interval fo...

Page 110: ...es 0 G0_Trigger_Mode_For_Edge_Gate 3 G0_Stop_Mode 0 G0_Counting_Once 0 G0_Command_Register G0_Up_Down 1 up counting G0_Bank_Switch_Enable 0 G0_Bank_Switch_Mode 0 Interrupt_A_Enable_Register G0_TC_Inte...

Page 111: ...not done print out the buffer values Example 3 This is the example for continuous pulse train generation It generates continuous pulses on the G_Out pin with three delay from the trigger pulse interv...

Page 112: ...0_Source_Select 0 G_In_TimeBase G0_Source_Polarity 0 rising edges G0_Gate_Select 5 PFI4 G0_OR_Gate 0 G0_Output_Polarity 0 active high G0_Gate_Select_Load_Source 0 G0_Mode_register G0_Output_Mode 2 tog...

Page 113: ...4 bits G0_Load_A pulse interval 1 3 G0_Load_B_Register G0_Load_B pulse width 1 3 G0_Command_Register G0_Bank_Switch_Start 1 if g_bank_to_be_used 0 g_bank_to_be_used 1 else g_bank_to_be_used 0 else inf...

Page 114: ...in the DAQ STC Technical Reference Manual for information about the analog trigger functionality of the DAQ STC The various modes Low Window High Window Middle Window high and low hysteresis are disc...

Page 115: ...parator The outputs of each comparator goes high when the input voltage is greater than the threshold The outputs of these two comparators are connected to the DAQ STC analog trigger inputs 0 and 1 Th...

Page 116: ...he 8 bit DAC and 12 bit DAC is illustrated in Chapter 5 of this manual in the Calibration DACs section The example uses low hysteresis mode and PGIA as the triggering source The low value is set to be...

Page 117: ...ADC_FIFO_Data_Register Do If AIFIFO not empty then read FIFO data while 100 samples have not been read Interrupt Programming Chapter 8 Interrupt Control in the DAQ STC Technical Reference Manual discu...

Page 118: ...l DMA channels A B and C There are three registers Channel A Mode Register address 0x03 Channel B Mode Register address 0x05 and Channel C Mode Register address 0x07 corresponding to these logical cha...

Page 119: ...DMA requests based on any of the following conditions FIFO empty FIFO less than half full FIFO not full Assert on FIFO half full and deassert on FIFO full For general purpose counter timers an interru...

Page 120: ...ng serviced the CPU can access the other buffer This way seamless data transfer is possible Dual channel DMA can be used in analog output or for the general purpose counter timers Only the AT MIO 16E...

Page 121: ...onment in which the board is used EEPROM The EEPROM is used to store all non volatile information about the board including the factory and user calibration constants The AT E Series boards use a XICO...

Page 122: ...the EEPROM could result in an access to the CalDACs but this is also not true The CalDACs will be updated only when the LdCalDAC 2 0 bit is pulsed Tables 5 1 5 2 5 3 and 5 4 show a selected portion of...

Page 123: ...ory CALDAC 3 value AI 8 bit 421 0 Factory CALDAC 2 value AI 8 bit 420 0 Factory CALDAC 5 bipolar value AO 8 bit 419 0 Factory CALDAC 7 bipolar value AO 8 bit 418 0 Factory CALDAC 6 bipolar value AO 8...

Page 124: ...DAQ Board Code 510 Revision Revision 509 Sub revision Sub revision 508 Year Year of last factory calibration 507 Month Month of last factory calibration 506 Day Day of last factory calibration 424 0 F...

Page 125: ...AC 6 unipolar value AO 8 bit 408 0 Factory CALDAC 8 unipolar value AO 8 bit 407 0 Factory CALDAC 10 unipolar value AO 8 bit 406 0 Factory CALDAC 9 unipolar value AO 8 bit 371 0 Start of the 5 user cal...

Page 126: ...8 bit 432 0 Factory CALDAC 1 value AI bipolar 8 bit 431 0 Factory CALDAC 8 value MSB AI unipolar 8 bit 430 0 Factory CALDAC 8 value LSB AI unipolar 8 bit 429 0 Factory CALDAC 2 value AI unipolar 8 bit...

Page 127: ...Reference LSB 438 0 Factory CALDAC 8 value MSB AI bipolar 437 0 Factory CALDAC 8 value LSB AI bipolar 436 0 Factory CALDAC 2 value AI bipolar 435 0 Factory CALDAC 3 value AI bipolar 434 0 Factory CAL...

Page 128: ...on and AD8522 for analog triggering The DAC8800 contains eight 8 bit DACs the DAC8043 contains one 12 bit DAC and the AD8522 contains two 12 bit DACs The Serial Command Register has five bits SerClk b...

Page 129: ...write a separate application using Calibrate_E_Series which is run only when the board needs new calibration constants Writing such an application allows the normal application to simply copy the cali...

Page 130: ...contains a manufacturer data sheet for the MSM82C55A CMOS programmable peripheral interface OKI Semiconductor This interface is used on the AT MIO 16DE 10 Copyright OKI Semiconductor 1993 Reprinted wi...

Page 131: ...Appendix A OKI MSM82C55A Data Sheet AT MIO E Series RLPM A 2 National Instruments Corporation...

Page 132: ...Appendix A OKI MSM82C55A Data Sheet National Instruments Corporation A 3 AT MIO E Series RLPM...

Page 133: ...Appendix A OKI MSM82C55A Data Sheet AT MIO E Series RLPM A 4 National Instruments Corporation...

Page 134: ...Appendix A OKI MSM82C55A Data Sheet National Instruments Corporation A 5 AT MIO E Series RLPM...

Page 135: ...Appendix A OKI MSM82C55A Data Sheet AT MIO E Series RLPM A 6 National Instruments Corporation...

Page 136: ...Appendix A OKI MSM82C55A Data Sheet National Instruments Corporation A 7 AT MIO E Series RLPM...

Page 137: ...Appendix A OKI MSM82C55A Data Sheet AT MIO E Series RLPM A 8 National Instruments Corporation...

Page 138: ...Appendix A OKI MSM82C55A Data Sheet National Instruments Corporation A 9 AT MIO E Series RLPM...

Page 139: ...Appendix A OKI MSM82C55A Data Sheet AT MIO E Series RLPM A 10 National Instruments Corporation...

Page 140: ...Appendix A OKI MSM82C55A Data Sheet National Instruments Corporation A 11 AT MIO E Series RLPM...

Page 141: ...Appendix A OKI MSM82C55A Data Sheet AT MIO E Series RLPM A 12 National Instruments Corporation...

Page 142: ...Appendix A OKI MSM82C55A Data Sheet National Instruments Corporation A 13 AT MIO E Series RLPM...

Page 143: ...Appendix A OKI MSM82C55A Data Sheet AT MIO E Series RLPM A 14 National Instruments Corporation...

Page 144: ...Appendix A OKI MSM82C55A Data Sheet National Instruments Corporation A 15 AT MIO E Series RLPM...

Page 145: ...Appendix A OKI MSM82C55A Data Sheet AT MIO E Series RLPM A 16 National Instruments Corporation...

Page 146: ...Appendix A OKI MSM82C55A Data Sheet National Instruments Corporation A 17 AT MIO E Series RLPM...

Page 147: ...es not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National In...

Page 148: ...office in your country contact the source from which you purchased your software to obtain support Country Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Be...

Page 149: ...___ Instruments used _________________________________________________________________ _______________________________________________________________________________ National Instruments hardware pro...

Page 150: ...___ Base I O address of other boards ____________________________________________________ DMA channels of other boards _____________________________________________________ Interrupt level of other bo...

Page 151: ..._____________________ _______________________________________________________________________________ _______________________________________________________________________________ __________________...

Page 152: ...10 9 micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 109 Symbols inverted bit negative logic if after a bit name ohms A A amperes AC alternating current A D analog to digital ADC A D converter AI...

Page 153: ...select bit Channel physical channel select bit ChanEnable DMA channel enable bit ChanType channel type bit CONVERT convert signal D D data bit D A digital to analog DAC D A converter DAC0OUT analog ch...

Page 154: ...bit DmaTcCClr DMA ternimal count C clear bit E EEPROM electrically erasable programmable read only memory EEPromCS EEPROM chip select bit EXTREF external reference signal ExtRef external reference for...

Page 155: ...reference bit H hex hexadecimal Hz hertz I Input analog input bit Int Ext Trig internal external analog trigger I O input output IRQ interrupt request signal ISA Industry Standard Architecture L LAST...

Page 156: ...put analog output bit P PFI0 Trig1 PFI 0 Trigger 1 signal PFI1 Trig2 PFI 1 Trigger 2 signal PGIA Programmable Gain Instrumentation Amplifier ppm parts per million PRETRIG pretrigger signal PROMOUT EEP...

Page 157: ...d bit SerData serial data bit SHIFTIN shift in signal SI scan interval counter SI2 sample interval START start signal STOP stop signal T TC terminal count TCIntEnable DMATC interrupt enable bit Transf...

Page 158: ...Glossary National Instruments Corporation G 7 AT MIO E Series RLPM V V volts Vref input voltage reference X X don t care bits...

Page 159: ...4 9 AI_Interrupt_Enable function DMA scanning example 4 17 interrupt scanning example 4 14 AI_Reset_All function 4 8 AI_Scan_Start function AMUX 64T examples sampling one channel 4 25 scanning eight...

Page 160: ...a Register 3 19 DAC1 Direct Data Register 3 20 overview 3 16 register map 3 2 analog output timing circuitry single point output 2 22 theory of operation 2 22 to 2 23 waveform generation 2 22 to 2 23...

Page 161: ...6 LastChan 3 10 LASTCHANNEL 2 12 Output C A 3 25 PROMOUT 3 7 ReGlitch 3 17 SerClk 3 6 5 1 5 8 SerDacLd0 3 5 5 8 SerDacLd1 3 5 5 8 SerDacLd2 3 5 SerData 3 6 5 8 TCIntEnable 3 22 3 23 Transfer 2 0 3 22...

Page 162: ...ter 3 23 Channel C Mode Register 3 24 ChanType 2 0 bit 3 12 Clear_FIFO function 4 8 configuration memory definition 2 9 multirate scanning without ghost table 2 17 Configuration Memory Clear Register...

Page 163: ...ion 4 4 DAQ_STC_Windowed_Mode_Write function 4 4 data acquisition timing circuitry 2 12 to 2 17 ADC timing figure 2 11 block diagram 2 8 data acquisition sequence timing 2 12 to 2 17 multirate scannin...

Page 164: ...support services B 1 to B 2 e mail support B 2 ESERFNCT c example file 4 4 ESERRLP h example file 4 4 event counting example 4 42 to 4 44 ExtRef bit 3 17 EXTSTROBE signal 2 23 to 2 24 F fax and telep...

Page 165: ...L bit 2 12 M manual See documentation Misc Command Register description 3 6 register map 3 2 Misc Register Group Misc Command Register 3 6 overview 3 4 register map 3 2 Serial Command Register 3 5 to...

Page 166: ...trigger acquisition 2 18 Program_DMA_Controller function 4 17 programmable gain instrumentation amplifier PGIA See PGIA programmable gain instrumentation amplifier programming analog triggering 4 49 t...

Page 167: ...18 DAC0 Direct Data Register 3 19 DAC1 Direct Data Register 3 20 overview 3 16 DAQ STC Register Group 3 27 4 1 DIO Register Group 3 26 DMA Control Register Group AI AO Select Register 3 25 Channel A...

Page 168: ...single point output analog output timing circuitry 2 22 single read timing data acquisition timing circuitry 2 11 to 2 12 SOURCE signal timing I O circuitry 2 24 START signal 2 12 START1 signal 2 18...

Page 169: ...11 to 2 12 timing of scan figure 2 13 timing I O circuitry 2 24 Transfer 2 0 bits Channel A Mode Register 3 22 Channel B Mode Register 3 23 Channel C Mode Register 3 24 trigger lines RTSI programming...

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