National Instruments AT-AI-16XE-10, Programmer'S Manual

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Chapter 3 Register Map and Descriptions — ADC FIFO Data Register
AT-MIO E Series RLPM 3-8 © National Instruments Corporation
Analog Input Register Group
The three registers making up the Analog Input Register Group control the analog input
circuitry and can be used to read the ADC FIFO contents. Reading the ADC FIFO Data
Register location transfers data from the AT E Series ADC data FIFO to the PC. Writing to
the Configuration Memory Low and Configuration Memory High Register locations sets up
channel configuration information for the analog input section. This information is necessary
for single conversions as well as for single- and multiple-channel data acquisition sequences.
ADC FIFO Data Register
The ADC FIFO Data Register returns the oldest ADC conversion value stored in the
ADC FIFO. Reading the ADC FIFO removes that value and leaves space for another
ADC conversion value to be stored. Values are shifted into the ADC FIFO whenever an
ADC conversion is complete unless the GHOST bit is set in that entry of the Configuration
Memory.
The ADC FIFO is emptied when all values it contains are read. The empty, half-full, and full
flags from the ADC data FIFO are available in a status register in the DAQ-STC. These flags
indicate when the FIFO is empty, half-full, or full, respectively. Whenever the FIFO is not
empty, the stored data can be read from the ADC FIFO Data register.
The values returned by reading the ADC Data Register are available in two different binary
formats: straight binary, which generates only positive numbers, or two’s complement binary,
which generates both positive and negative numbers. The binary format used is determined
by the mode in which the ADC is configured. Following is the bit pattern returned for either
format:
Address: Base a 1C (hex)
Type: Read-only
Word Size: 16-bit
Bit Map:
15 14 13 12 11 10 9 8
D15 D14 D13 D12 D11 D10 D9 D8
7 6 5 4 3 2 1 0
D7 D6 D5 D4 D3 D2 D1 D0