Motorola VRS750, Service Manual

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Single Tone Encoder
The VRS750 Single Tone Encoder (U100-1, U124-3, U124-2, and U124-
4) is used to produce a tone which is transmitted by the transceiver
when the VRS750 is activated. Other VRS750 repeaters that are on in
the operating area receive this Single Tone transmission. The other
repeaters will then increment their priority counters by one while the
transmitting VRS750 goes to delay state zero and becomes the priority
repeater.
When the VRS750 is in transmit mode for Single Tone, the
microcontroller generates a square wave at a set frequency of 847.5Hz
to the SNGL_TX_DATA (J30-6) pin. The control signal, TONES-
MOBILE_AUD, is set to a High state to allow the Single Tone signal to
be routed to the input of the Single Tone Filter. The Single Tone Filter
is a band pass filter that allows frequencies between 300Hz and 1.7
kHz. U124-4, R126 and R127 are for gain adjustment. The resulting
sine wave is then sent to the transceiver to be transmitted on EXT_MIC
(J30-19).
This circuit is also used when the transceiver generates various VRS750
acknowledgment tones.
Single Tone Decoder
The VRS750 Single Tone Decoder (U100-1, U124-3, U124-2, and
U124-1) detects other Single Tone transmissions, then increments the
priority counter.
VRS_TX*_RX from the microprocessor is set to a High state when the
VRS750 is in the Single Tone Decode mode (receive mode). When this
signal is high, U101-2 allows receive audio (URX_SND, J30-11) to pass
to buffer U100-1. The output of the buffer drives the low-pass filter
that is also used in the encoder circuit. U124-1 and the associated
diodes, D100 and D101, produce a square wave which is divided down
to 3.3V by R172 and R173. This signal, SNGL_DET(J30-12), is then
sampled by the microprocessor to determine if Single Tone is present.
Boot Control
Circuitry
The firmware for the VRS750 is stored in the transceiver’s Flash
memory. This firmware can be programmed using the VRS750
Upgrade Tool (refer to “VRS750 Upgrade Kit,” in Chapter 2). Prior to
programming the firmware, the microprocessor must be placed into
bootstrap mode.
To place the microprocessor into bootstrap mode, it must be reset
while the BOOT-CNTRL (J30-28) pin is grounded. This pin is grounded
when the programming cable is connected and the flash adapter
switch is turned to the “A” position.
When the BOOT-CNTRL line is grounded, Q100 which controls U102
and U105, is opened and 9.6V passes through U102-2 to the base of
Q112. Q113 opens and disconnects SW7.5 V from 7.5 V. At this point
there is no supply voltage to the transceiver.
Meanwhile, 9.6V is also applied to the base of Q112 thus charging up
capacitor C182. After approximately 1.5 seconds, C182 is charged to a
voltage that saturates Q111, causing Q112 to open and Q113 to turn