OR CIRCUIT DESCRIBED HEREIN.
APPLICATION OR USE OF ANY PRODUCT
MOTOROLA DOES NOT ASSUME ANY
RELIABILITY, FUNCTION, OR DESIGN.
ANY PRODUCTS HEREIN TO IMPROVE
CHANGES WITHOUT FURTHER NOTICE TO
LIABILITY ARISING OUT OF THE
MOTOROLA RESERVES THE RIGHT TO MAKE
6501 WILLIAM CANNON DRIVE WEST
AUSTIN, TEXAS 78735 USA
MICROPROCESSOR AND MEMORY
DRAWN BY:
DATE:
TECHNOLOGIES GROUP
DESIGN ENGINEER:
PROJECT LEADER:
DATE:
DATE:
TITLE:
MPB916R3C
SCHEMATIC -
KATSUTOSHI NAGAI
04/01/97
A
REV:
DWG. NO.
SIZE
GEDABV:
SHEET
DWG. NO.
REV:
GEDTTL:
A
D
31
2
C
B
4
A
D
C
31
2
4
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BOARD
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TITLE & REVISION STATUS
1
TABLE OF CONTENTS
2
NOTES
6
MCU & CLOCK
4
MODULAR ACTIVE PROBE INTERCONNECT P1 & P3
3
BYPASS CAPACITORS, CLEAN POWER & SIGNAL FILTERS
5
MODULAR ACTIVE PROBE INTERCONNECT P2 & P4
7
PULLUPS/PULLDOWNS/PERSONALITY ID
8
SIGNAL CROSS REFERENCES
ZONE
REV
DESCRIPTION
APPROVED
REVISIONS
DATE
ORIGINAL RELEASE
O
04/01/97
KATSUTOSHI NAGAI
