MEVB SUPPORT INFORMATION
4-2
M68MPB16R3UM/D
Table 4-1. Logic Analyzer Connector J7 Pin Assignments
Pin
Mnemonic
Signal
1, 2
SPARE
No connection
3
OE(ALL)
I/O PRU OUTPUT ENABLE – Input, active high;
when low disables
all
PRU outputs.
4 – 11
PEPAR7 –
PEPAR0
PEPAR OUTPUTS – Output signals that show the
complement
(negated contents) of the PEPAR
register.
12 – 19
PE7 – PE0
PORT E I/O SIGNALS – PRU replacement of the port
E function.
20
GND
GROUND
Table 4-2. Logic Analyzer Connector J8 Pin Assignments
Pin
Mnemonic
Signal
1, 2
SPARE
No connection
3
OE(ABG)
I/O PRU OUTPUT ENABLE – Input, active high;
when low disables port A, port B, and port G outputs.
4 – 11
PA7 – PA0
PORT A I/O SIGNALS – PRU replacement of the port
A function.
12 – 19
PB7 – PB0
PORT B I/O SIGNALS – PRU replacement of the port
B function.
20
GND
GROUND
