MEVB SUPPORT INFORMATION
4-12
M68MPB16R3UM/D
Table 4-12. Logic Analyzer Connector J18 Pin Assignments
Pin
Mnemonic
Signal
1 – 4
SPARE
No connection
5
MISO
MASTER-IN, SLAVE-OUT – Serial input to SPI in
master mode; serial output from SPI in slave mode.
6
MOSI
MASTER-OUT, SLAVE-IN – Serial output from SPI in
master mode; serial input to SPI in slave mode.
7
SCK
SPI SERIAL CLOCK – In master mode, the clock
signal from the SPI; in slave mode the clock signal to
the SPI.
8
SS
SLAVE SELECT – Bi-directional, active-low signal
that puts the SPI in slave mode.
9
RXDB
RECEIVE DATA B – Serial data input line to serial
communication interface B.
10
TXDB
TRANSMIT DATA B– Serial data output line to serial
communication interface B.
11
RXDA
RECEIVE DATA A – Serial data input line to serial
communication interface A.
12
TXDA
TRANSMIT DATA A – Serial data output line to serial
communication interface A.
13 – 16
GND
GROUND
17 – 19
SPARE
No connection
20
GND
GROUND
