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Motorola M-CORE MMC2001 Series, Reference Manual

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MOTOROLA

INTEGER CPU

MMC2001 

2-14

REFERENCE MANUAL

2.8.6 Bus Exception Cycles

The M•CORE bus interface requires assertion of TA from an external device to signal
that a bus cycle is complete. External circuitry can provide TEA when no device
responds to indicate that an error condition is associated with an access. This allows
the cycle to terminate and the processor to enter exception processing for the error
condition if appropriate.

To control termination of a bus cycle for a bus error condition properly, TA and TEA
must be asserted and negated about the same rising edge of CLK. 

The system hardware can use the TEA signal to abort the current bus cycle when a
fault is detected. When the processor recognizes a bus error condition for an access,
the access is terminated immediately.

When a bus cycle is terminated with a bus error, the M•CORE can enter access error
exception processing immediately following the bus cycle, or it can defer processing
the exception. The instruction pre-fetch mechanism requests instruction words from
the instruction memory unit before it is ready to execute them. If a bus error occurs on
an instruction fetch, the processor does not take the exception until it attempts to use
the instruction. If an intervening instruction causes a branch or if a task switch occurs,
the access error exception for the unused access does not occur.

A bus error termination for any write or read access that references data specifically
requested by the execution unit causes the processor to begin exception processing
immediately.

Table 2-4 Termination Result Summary

TA

TEA

Result

Don’t Care

Low

Bus Error — terminate and take bus error exception if appropriate

Low

High

Normal cycle terminate and continue

High

High

Insert wait states

 

   

  

Freescale Semiconductor,

 I

                                               

Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

nc.

..

Summary of Contents for M-CORE MMC2001 Series

Page 1: ...reate a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of...

Page 2: ...bit or bits means to establish logic level one on the bit or bits To clear a bit or bits means to establish logic level zero on the bit or bits LSB means least significant bit or bits MSB means most significant bit or bits Refer ences to low and high bytes are spelled out A signal is asserted when it is in its active or true state regardless of whether that state is represented by a high or low vo...

Page 3: ...MOTOROLA MMC2001 iv REFERENCE MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 4: ...ON 3 SYSTEM MEMORY MAP 3 1 Overview 3 1 3 2 Peripheral Module Address Allocation 3 1 3 3 Peripheral Module Interface Operation 3 2 3 4 Peripheral Module Address Assignment 3 2 SECTION 4 SIGNAL DESCRIPTIONS 4 1 Overview 4 1 4 2 Signal Index 4 2 4 3 Bus Signals 4 4 4 3 1 Address Bus ADDR 19 0 4 4 4 3 2 Data Bus DATA 15 0 4 4 4 3 3 Output Enable OE 4 4 4 3 4 Read Write Enable R W 4 4 4 3 5 Enable Byt...

Page 5: ...Signals 4 7 4 9 1 Receive Data RxD0 RxD1 4 7 4 9 2 Transmit Data TxD0 TxD1 4 7 4 9 3 Clear to Send CTS0 4 7 4 9 4 Request to Send RTS0 4 8 4 10 Serial Peripheral Interface Module Signals 4 8 4 10 1 SPI Data Master Out Slave In SPI_MOSI 4 8 4 10 2 SPI Data Master In Slave Out SPI_MISO 4 8 4 10 3 SPI Serial Clock SPI_CLK 4 8 4 10 4 SPI Enable SPI _EN 4 8 4 10 5 SPI General Purpose Output SPI _GP 4 8...

Page 6: ...6 7 5 3 Programmable Output Generation 7 6 7 5 4 Bus Watchdog Operation 7 6 7 5 5 Error Conditions 7 6 7 5 6 Show Cycles 7 7 7 6 EIM Programming Model 7 7 7 6 1 Chip Select Control Registers 7 7 7 7 EIM Configuration Register 7 11 7 8 External Bus Timing Diagrams 7 13 SECTION 8 CLOCK MODULE AND LOW POWER MODES 8 1 Overview 8 1 8 2 Low Power Modes 8 4 8 2 1 CPU Core Low Power Modes 8 4 8 2 2 Periph...

Page 7: ...7 Watchdog Timer in Debug Mode 9 10 9 5 8 Watchdog Timer Programming Model 9 10 9 6 Interval Timer PIT 9 11 9 6 1 PIT Operation 9 12 9 6 2 PIT as a Set and Forget Timer 9 12 9 6 3 PIT as a Free Running Timer 9 13 9 6 4 Interval Timer Registers 9 13 9 6 5 PIT Control Status Register ITCSR 9 14 9 6 6 PIT Data Register ITDR 9 15 9 6 7 PIT Alternate Data Register ITADR 9 16 9 6 8 PIT in Low Power Mode...

Page 8: ... 4 5 UART BRG Register UBRGR 11 13 11 4 6 UART Status Register USR 11 14 11 4 7 UART Test Register UTS 11 15 11 5 GPIO Pins and Registers 11 16 11 5 1 UART Port Control Register UPCR 11 16 11 5 2 UART Data Direction Register UDDR 11 16 11 5 3 UART Port Data Register UPDR 11 17 11 6 Data Sampling Technique on the Receiver 11 17 11 7 UART Operation in Low Power System Modes 11 23 11 8 UART Operation...

Page 9: ...r EPPAR 13 2 13 3 2 Edge Port Data Direction Register EPDDR 13 3 13 3 3 Edge Port Data Register EPDR 13 3 13 3 4 Edge Port Flag Register EPFR 13 4 SECTION 14 KEYPAD PORT 14 1 Overview 14 1 14 2 KPP Pin Description 14 2 14 2 1 Input Pins 14 2 14 2 2 Output Pins 14 2 14 3 KPP Programming Model 14 2 14 3 1 Keypad Control Register KPCR 14 2 14 3 2 Keypad Status Register KPSR 14 3 14 3 3 Keypad Data Di...

Page 10: ...nCE Interface Signals 16 5 16 5 1 Internal Debug Request Input IDR 16 5 16 5 2 CPU Debug Request DBGRQ 16 5 16 5 3 CPU Debug Acknowledge DBGACK 16 5 16 5 4 CPU Breakpoint Request BRKRQ 16 5 16 5 5 CPU Address Attributes ADDR ATTR 16 5 16 5 6 CPU Status PSTAT 16 5 16 5 7 OnCE Debug Output DEBUG 16 6 16 6 OnCE Controller Registers 16 6 16 6 1 OnCE Command Register OCMR 16 6 16 6 2 OnCE Control Regis...

Page 11: ...erved Test Control Registers Reserved MEM_BIST FTCR LSRL 16 21 16 13 Serial Protocol Description 16 21 16 13 1 OnCE Commands 16 21 16 14 Target Site Debug System Requirements 16 21 16 15 Interface Connector For JTAG OnCE Serial Port 16 22 APPENDIX A ELECTRICAL CHARACTERISTICS A 1 Maximum Ratings A 1 A 2 DC Electrical Specifications A 1 A 3 Clock Input Specifications A 2 A 4 AC Electrical Specifica...

Page 12: ... 14 C 4 3 Keypad Data Direction Register KDDR C 15 C 4 4 Keypad Data Register KPDR C 15 C 5 EIM Programming Model C 16 C 5 1 Chip Select Control Registers C 16 C 5 2 EIM Configuration Register C 20 C 6 PWM Module C 22 C 6 1 PWM Control Register C 23 C 6 2 PWM Period Register C 25 C 6 3 PWM Width Register C 26 C 6 4 PWM Counter Register C 27 C 7 Edge Port Programming Model C 27 C 7 1 Edge Port Pin ...

Page 13: ...10 4 Memory Address Latch MAL C 51 C 10 5 Breakpoint Address Base Registers BABA BABB C 51 C 10 6 Breakpoint Address Mask Registers BAMA BAMB C 51 C 10 7 Breakpoint Address Comparators C 51 C 10 8 Memory Breakpoint Counters MBCA MBCB C 51 C 10 9 Program Counter Register PC C 51 C 10 10 Instruction Register IR C 52 C 10 11 Control State Register CTL C 52 C 10 12 Write Back Bus Register WBBR C 53 C ...

Page 14: ...EDC 1 7 19 7 12 Peripheral Read Access CSA 1 WSC 5 7 20 7 13 Peripheral Write Access CSA 1 WSC 5 7 21 7 14 Read and Write Fast Memory Access CSA 0 WSC 0 WWS 0 7 22 8 1 MMC2001 Clock Module 8 3 9 1 Reset Functional Block Diagram 9 2 9 2 Reset Source Register 9 3 9 3 TOD Block Diagram 9 4 9 4 TOD Control Status Register 9 5 9 5 TOD Seconds Register 9 6 9 6 TOD Fraction Register 9 7 9 7 TOD Seconds A...

Page 15: ...2 1 ISPI Channel Block Diagram 12 1 12 2 Timing Diagram of ISPI 8 Bit Operation 12 2 12 3 ISPI Data Register 12 5 12 4 ISPI Control Register 12 5 12 5 ISPI Interval Control Register 12 8 12 6 ISPI Status Register 12 8 13 1 External Interrupt GPIO Block Diagram 13 1 13 2 Edge Port Pin Assignment Register 13 2 13 3 Edge Port Data Direction Register 13 3 13 4 Edge Port Data Register 13 3 13 5 Edge Po...

Page 16: ... A 8 SPI Manual Interval Mode Timing PHA 0 A 8 A 9 SPI Manual Interval Mode Timing PHA 1 A 8 A 10 Test Clock Input Timing A 9 A 11 TRST Timing A 9 A 12 Test Access Port Timing A 10 B 1 144 Lead Plastic Thin Quad Flat Pack Pin Assignment B 1 C 1 Interrupt Source Register C 2 C 2 Normal Interrupt Enable Register C 3 C 3 Fast Interrupt Enable Register C 3 C 4 Normal Interrupt Pending Register C 4 C 5...

Page 17: ...C 31 Edge Port Flag Register C 29 C 32 ISPI Data Register C 30 C 33 ISPI Control Register C 31 C 34 ISPI Interval Control Register C 33 C 35 ISPI Status Register C 34 C 36 UART Receive Register C 36 C 37 UART Transmit Register C 37 C 38 UART Control Register 1 C 38 C 39 UART Control Register 2 C 40 C 40 UART BRG Register C 42 C 41 UART Status Register C 42 C 42 UART Test Register C 44 C 43 UART Po...

Page 18: ...roller Address Map 10 2 10 2 Interrupt Source Assignment 10 6 11 1 UART Module Address Map 11 6 11 2 TxFL Field Settings 11 9 11 3 RxFL Field Settings 11 10 11 4 UART Pins GPIO Assignment 11 16 11 5 UART Low Power Mode Operation 11 23 12 1 ISPI Module Address Map 12 4 12 2 BAUD RATE Field Settings 12 7 12 3 CLOCK COUNT Field Settings 12 7 12 4 ISPI Low Power Mode Operation 12 11 13 1 GPIO Edge Por...

Page 19: ...eld Settings C 19 C 8 Chip Select Address Range C 20 C 9 Show Cycle Enable Field Settings C 22 C 10 PWM Address Map C 22 C 11 Clock Select Field Values C 25 C 12 GPIO Edge Port Address Map C 27 C 13 EPPAx Field Settings C 28 C 14 Interval Mode Serial Peripheral Interface Address Map C 30 C 15 BAUD RATE Values C 32 C 16 CLOCK COUNT Values C 33 C 17 UART Module Address Map C 35 C 18 TxFL Field Setti...

Page 20: ...well as an alarm clock function Watchdog timer resets the chip to recover from system failure Reset unit provides low voltage detection input and backup power switching for SRAM and the time of day timer Periodic interrupt timer Universal Asynchronous Receiver Transmitter Module UART Two independent UART channels Asynchronous operation Baud rate generation Infrared IR interface support 16 bit gene...

Page 21: ...vided with independent power sup ply connections to allow 3 3 V I O levels while operating internal logic at 2 0 V for lower power consumption Figure 1 1 MMC2001 Block Diagram M CORE 32 Bit 32 Kbyte SRAM 20 Bit Address Bus 16 Bit Data Bus Control CLK Watchdog Memory Controller TOD Reset ISPI OSC 256 Kbyte ROM Periodic Interval OnCE PWM x 6 UART x 2 Timer GEN GPIO Keypad Interrupt RISC CPU Peripher...

Page 22: ...equency M CORE is a streamlined execution engine that provides many of the same perfor mance enhancements as mainstream reduced instruction set computer RISC designs Fixed length instruction encoding and a strict load store architecture mini mize control complexity and overhead The goal of minimizing the overhead of mem ory system energy consumption is achieved by adopting a relatively short 16 bi...

Page 23: ...e and miscellaneous support hardware for multiplication and multiple register loads and stores Arithmetic and logical operations are executed in a single cycle with the exception of the multi ply signed divide and unsigned divide instructions The multiply instruction is imple mented with a 2 bit per clock overlapped scan modified Booth algorithm with early out capability to reduce execution time f...

Page 24: ...nstructions provide controlled access to operating system services for user programs Access to special control registers is also precluded in user mode When the S bit in the PSR is set the processor executes instructions in the supervi sor mode Bus cycles associated with an instruction indicate either supervisor or user access depending on the mode The processor uses the user programming model dur...

Page 25: ...gisters is pro vided to save the state of the PSR and the program counter at the time an exception occurs A separate set of shadow registers is provided for fast interrupt support to minimize context saving overhead Five scratch registers are provided for supervisor software use in handling exception events A single register is provided to alter the base address of the exception vector table Two r...

Page 26: ...d at address 0 Bits are numbered within a word start ing with bit 31 as the most significant bit Figure 2 2 Data Organization in Memory Figure 2 3 Data Organization in Registers Byte 0 Byte 1 Byte 2 Byte 3 Word at 0 31 0 Byte 4 Byte 5 Byte 6 Byte 7 Word at 4 Byte 8 Byte 9 Byte A Byte B Word at 8 Byte C Byte D Byte E Byte F Word at C Byte Signed Byte S S S S S S S S S S S S S S S S S S S S S S S S ...

Page 27: ... logical instructions is provided as well as instruction support for bit operations byte extrac tion data movement control flow modification and a small set of conditionally exe cuted instructions which can be useful in eliminating short conditional branches Table 2 1 is an alphabetized listing of the M CORE instruction set Refer to the M CORE Reference Manual MCORERM AD for more details on instru...

Page 28: ...I Jump Jump Indirect Jump to Subroutine Jump to Subroutine Indirect LD BHW LDM LDQ LOOPT LRW LSL LSR LSLC LSRC LSLI LSRI Load Load Multiple Registers Load Register Quadrant Decrement with C Bit Update and Branch if Condition True Load Relative Word Logical Shift Left and Right Logical Shift Left and Right Update C Bit Logical Shift Left and Right by Immediate MFCR MOV MOVI MOVF MOVT MTCR MULT MVC ...

Page 29: ... bus interfaces The M CORE port size is fixed at 32 bits External devices can accept or provide eight or 16 bits in parallel and must follow the handshake protocol described in this section The number of bits accepted or provided during a bus transfer is defined as the transfer size The M CORE uses the address bus to specify the address for the transfer and the data bus to transfer the data Contro...

Page 30: ...ust be stable during the sample windows defined in Figure 2 4 If an input makes a transition during the win dow time period the level recognized by the M CORE is not predictable Outputs from the M CORE change on one of the two clock edges depending on the signal class Figure 2 4 Signal Relationships to Clocks 2 8 2 Bus Signals Figure 2 5 shows the M CORE bus signals arranged by functional group CL...

Page 31: ...quent sections Signal direction is relative to the M CORE ADDR 31 0 R W TREQ TSIZ 1 0 TC 2 0 TA DATA 31 0 TEA ABORT 32 1 1 2 3 1 32 1 1 Address and Transfer Attributes Data Transfer Status Termination TBUSY 1 Transfer Request Transfer Busy LPMD 1 0 2 Power Management DBGACK 1 Debug Acknowledge Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www free...

Page 32: ... that an access is in progress This signal is driven for the duration of a cycle and may be held asserted for multiple transfers Data DATA 31 0 Data Bus 32 High O Driven by the M CORE when it owns the bus and it initi ated a write transaction to a slave device Eight byte 16 halfword or 32 word bits of data can be transferred per access I Driven by the slave in a read transaction Eight byte 16 half...

Page 33: ...rive the ADDR 1 0 address lines to a value which is not representative of an aligned transfer but expects aligned data to be transferred ADDR 1 0 should be selectively ignored by external logic depending on the size of the transfer The data multiplexer takes the four bytes of the core interface data bus and routes them to their required positions to interface properly to memory or peripherals The ...

Page 34: ...rol signals The address and data buses are parallel non multiplexed buses that support aligned byte halfword and word transfers All bus input and output signals are sampled or driven with respect to one of the edges of the CLK signal The M CORE moves data on the bus by issuing control signals and using a handshake protocol to ensure correct data movement Access requests are generated in an overlap...

Page 35: ...r the M CORE can enter access error exception processing immediately following the bus cycle or it can defer processing the exception The instruction pre fetch mechanism requests instruction words from the instruction memory unit before it is ready to execute them If a bus error occurs on an instruction fetch the processor does not take the exception until it attempts to use the instruction If an ...

Page 36: ... on 4096 byte bound aries Peripherals that require additional address space e g for buffers are assigned additional 4 Kbyte blocks In this case peripherals are located on a 2n address boundary corresponding to the size of the block Within a 4 Kbyte block peripheral registers may be incompletely decoded such that the register map repeats throughout the entire block or the peripheral may return unde...

Page 37: ...cated on 4096 byte boundaries Table 3 2 defines the address assignment for the on chip components Table 3 2 MMC2001 Address Map Address Range Hex Use Access 00000000 0003FFFF On Chip ROM Array Supervisor Selective User 00040000 000FFFFF ROM Echoes Supervisor Selective User 00100000 0FFFFFFF Not Used Access causes transfer error 10000000 10000FFF Interrupt Controller Supervisor Only 10001000 10001F...

Page 38: ...ional Signal Groups KPP INT 7 0 Edge ADDR 19 0 DATA 15 0 CLK GEN XOSC XTAL OSC EXOSC TMS TDI OnCE TDO TCK TxD1 TSIZ0 RxD1 TSIZ1 EB0 R W OE EB1 MOD CLKOUT CPU Peripheral SRAM TEST PWM CLKIN ROW 7 0 COL 7 0 CTS0 PSTAT3 RTS0 PSTAT2 ISPI SPI_MISO SPI_MOSI SPI_EN SPI_CLK Port PWM 5 0 TxD0 PSTAT0 RxD0 PSTAT1 TRST DE VSTBY VBATT CS 2 0 CS3 SPI_GP Timer Reset Module RSTIN LVRSTIN RSTOUT STBY UART1 UART0 R...

Page 39: ...O OL Programmable clock output XOSC 1 O 32 768 kHz XTAL output EXOSC 1 I 32 768 kHz XTAL input MOD 1 I Boot ROM control RSTOUT 1 O Resets external components RSTIN 1 I Initiates system reset LVRSTIN 1 I Low voltage supply switching control Debug and Test Port Control TMS 1 I 47 K pull up Test mode select TDI 1 I 47 K pull up Test data input TDO 1 O Test data output TCK 1 I 47 K pull up Test clock ...

Page 40: ...mory control Debug JTAG supply CGND 1 I External memory control Debug JTAG GND DVDD 2 I External memory data supply DGND 2 I External memory data GND FVDD 1 I Clock Clock outputs supply FGND 1 I Clock Clock outputs GND GVDD 2 I Keypad port Interrupts supply GGND 2 I Keypad port Interrupts GND HVDD 1 I UART ISPI supply HGND 1 I UART ISPI GND JVDD 1 I PWM supply JGND 1 I PWM GND XVDD 1 I Oscillator ...

Page 41: ... the current bus access is a read or write 4 3 5 Enable Byte 1 EB1 This active low output pin is active during an operation to data bits DATA 7 0 It may be configured to assert for both read and write cycles or for write cycles only 4 3 6 Enable Byte 0 EB0 This active low output pin is active during an operation to data bits DATA 15 8 It may be configured to assert for both read and write cycles o...

Page 42: ...re the connections for an external crystal to the internal oscillator circuit for generation of the internal LOW_REFCLK EXOSC is the input pin and XOSC is the output 4 5 2 Clock Input CLKIN This input pin provides the HI_REFCLK clock source to the CPU and internal periph erals 4 5 3 Clock Output CLKOUT This output pin provides an external clock source either the LO_REFCLK or the HI_REFCLK 4 6 Debu...

Page 43: ...inish the current instruction being executed save the instruction pipeline information enter debug mode and wait for commands to be entered from the serial debug input line This pin is asserted as an output for several clock cycles when the CPU enters debug mode as a result of a debug request or as a result of meeting a breakpoint condition If used to enter debug mode DE must be negated after the ...

Page 44: ... the least significant bit received first RxD0 is used to provide the PSTAT1 internal status signal when the PSTEN bit in the EIM configuration register is set In this case it operates as an active high PSTAT1 output RxD1 is used to provide the TSIZ1 internal status signal when the SZEN bit in the EIM configuration register is set In this case it operates as an active high TSIZ1 out put 4 9 2 Tran...

Page 45: ...12 INTERVAL MODE SERIAL PERIPHERAL INTERFACE for more information on these signals 4 10 1 SPI Data Master Out Slave In SPI_MOSI This signal is the serial data output from the SPI in master mode and the serial data input in slave mode 4 10 2 SPI Data Master In Slave Out SPI_MISO This signal is the serial data input to the ISPI in master mode and the serial data out put in slave mode 4 10 3 SPI Seri...

Page 46: ... capability All power supply pins must have adequate bypass capacitance for high frequency noise suppression 4 12 1 Positive Supply VDD This pin supplies positive power to the chip 4 12 2 Ground GND This pin is the negative supply ground to the chip 4 12 3 Standby Battery Power VBATT This pin supplies positive battery standby power to the chip 4 12 4 Standby Power Filter VSTBY This pin is used to ...

Page 47: ...MOTOROLA SIGNAL DESCRIPTIONS MMC2001 4 10 REFERENCE MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 48: ...tics of this imple mentation may change for future versions of the M CORE family External control is provided to disable the on chip ROM for system debugging pur poses via a control input to the chip When asserted the MOD input signal causes the on chip ROM to be disabled for the initial program counter fetch out of reset and the chip select module to dedicate the CS0 output for an external boot R...

Page 49: ...sed on the state of the M CORE PSR S bit Attempted cycles to a protected ROM address space are terminated with a TEA response to the CPU 5 3 Applications The ROM module can be used to store Reset boot code Frequently accessed code Table of constants Revision and identification registers for all MMC2001 peripherals Self test diagnostic code Freescale Semiconductor I Freescale Semiconductor Inc For ...

Page 50: ...future versions of the M CORE family The SPRAM control bit in the EIM configuration register allows selective access pro tection to be applied to the RAM See 7 7 EIM Configuration Register This bit may be used to control access to the RAM based on the state of the M CORE PSR S bit Attempted cycles to a protected RAM address space are terminated with a TEA response to the CPU The SRAM module is par...

Page 51: ...MOTOROLA STATIC RAM MODULE MMC2001 6 2 REFERENCE MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 52: ...rogrammable data port size for each chip select Control for external internal boot ROM device selection Bus watchdog counter for all bus cycles Programmable general output capability for unused chip select outputs Show cycles to allow internal bus cycles to be monitored externally Figure 7 1 EIM Block Diagram 7 2 Signals 7 2 1 Address Bus The ADDR 19 0 signals are address bus outputs used to addre...

Page 53: ...0 7 2 5 Boot Mode The MOD input pin selects the initial CPU boot mode during hardware reset If this pin is driven to a logic low level four LOW_REFCLK clock cycles before RSTOUT negation then the internal ROM will be disabled and the CPU will fetch the first word from offset 0x0 of the external Flash memory which is located at the abso lute address 0x2D00000 in the CPU address space The internal R...

Page 54: ...When disabled these pins can be used as programmable general purpose outputs 7 2 6 3 Chip Select 3 CS3 This active high output signal is asserted based on a decode of the internal address bus bits ADDR 31 24 of the access address When disabled this pin can be used as a programmable general purpose output 7 3 Chip Select Address Range Table 7 1 specifies the address range for each chip select outpu...

Page 55: ...s It does not support misaligned transfers ADDR 19 0 RAM 128K X 8 RAM 64K X 16 Flash 512K X 16 ADDR 16 0 ADDR 16 0 ADDR 15 0 ADDR 16 1 ADDR 19 1 ADDR 15 0 LB UB EB0 CS0 CS3 DATA 15 0 DATA 15 0 DATA 15 0 DATA 7 0 DATA 7 0 ADDR0 E CS CS CS WE WE WE R W RS OE OE OE OE EIM CS2 CS1 LCD Control R W OE OE EB1 R W EB1 R W EB1 EB0 DATA 7 0 R W Freescale Semiconductor I Freescale Semiconductor Inc For More ...

Page 56: ...ripher als Table 7 2 lists the combination of TSIZ ADDR 1 0 signals and DSZ bits that are used for each possible transfer size alignment and port width The bytes labeled with a dash are not required they are ignored on read transfers and driven with undefined data on write transfers Table 7 2 Interface Requirements for Read and Write Cycles Transfer Size Signal Encoding Port Width Active Interface...

Page 57: ...ngth of all requested accesses from the CPU If an access does not terminate i e the bus watchdog timer does not receive an internal TA or TEA within 128 clocks of being initiated the watchdog timer expires and forces the access to be terminated by asserting a TEA signal to the CPU The bus watchdog timer is automatically reset to a count of zero after the termination of each access If an internal C...

Page 58: ... The layout of the control register is slightly different for the CS0 output which does not support the programmable output function For CS1 CS3 control registers bits two to 15 i e bits other than the PA and CSEN bits are undefined at reset Access these registers with 32 bit loads and stores only Figure 7 3 CS0 Control Register Table 7 3 EIM Memory Map Address Use Access 10004000 CS0 Control Regi...

Page 59: ...0 for access to fast SRAM devices one clock read and write access CSA 0 WSC 0001 and WWS 0 for access to normal SRAM two clock read and write access CSA 0 WSC 0001 and WWS 1 for access to Flash memory two clock read access and three clock write access EDC CSA and WSC to the appropriate number for access to an LCD controller CS1CR CS1 Control Register 10004004 CS2CR CS2 Control Register 10004008 CS...

Page 60: ...cle is a read cycle to the same CS bank CSA Chip Select Assert This bit is used for devices that require additional address setup time and additional address data hold times It determines when the chip select is asserted and whether an idle cycle is inserted between back to back external transfers If WSC 0000 this bit is ignored 0 Chip select is asserted normally i e as early as possible No idle c...

Page 61: ...ble Byte Control This bit is used to indicate which access types are allowed to assert the enable byte outputs EB 0 1 0 Read and write accesses are both allowed to assert the EB 0 1 outputs thus configuring them as byte enables 1 Only write accesses are allowed to assert the EB 0 1 outputs thus configur ing them as byte write enables The EB 0 1 outputs must be configured as byte write enables for ...

Page 62: ...disabled the pin is a general purpose output controlled by the value of the PA control bit When CSEN0 is clear CS0 is inactive 1 Chip select is enabled and is asserted when an access address falls within the range specified by the memory map in Table 7 1 With the exception of CS0 this bit is cleared by reset disabling the chip select output pin CSEN0 is set at reset to allow CS0 to select from an ...

Page 63: ... mode accesses are prohibited An attempted access to the internal RAM in user mode will result in TEA assertion to the CPU SPROM Internal ROM Supervisor Protect This bit is used to restrict accesses to the internal ROM space if the access is attempted in the user mode of CPU operation On reset this bit is set 0 User mode accesses are allowed to the internal ROM 1 User mode accesses are prohibited ...

Page 64: ...l termination to the CPU during idle cycles caused by EDC or CSA being set follows normal operation as shown in Figure 7 11 Figure 7 12 and Figure 7 13 This means that internal transfers that occur dur ing EDC CSA idle cycles will not be visible externally 10 Show cycles enabled Internal termination to the CPU during idle cycles caused by EDC or CSA being set is delayed by one clock This ensures t...

Page 65: ...ess CSA 0 WSC 1 MCU ADDR MCU R W MCU TREQ CS OE EB 0 1 DATA 15 0 MCU TA ADDR 19 0 MCU DATA W W S3 S1 S1 XXX XX XXX XXX XXX CLK S2 addr V1 addr V2 addr V1 addr Vx R R R W OEA 1 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 66: ...cess CSA 0 WSC 1 WWS 0 MCU ADDR MCU R W MCU TREQ CS EB 0 1 DATA 15 0 MCU TA ADDR 19 0 MCU DATA S2 W W S3 S1 S1 X XXX XXX XXX CLK addr V1 addr V2 addr Vx W addr V1 W WEN 1 R W Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 67: ...ddr V1 CS S1 W W OE EB 0 1 DATA 15 0 MCU TA addr V2 addr V1 2 CS1 XX addr V2 XX addr Vx XX W W S5 S1 addr Vy XX addr V2 XX S2 W W S2 CS2 ADDR 19 0 MCU DATA READ READ XXX READ XXX Word R XX CLK Halfword Halfword S4 S3 addr Vy XX R W OEA OEA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 68: ... W EB 0 1 DATA 15 0 MCU TA CS1 W S5 S1 S2 W W S2 CS2 WEN ADDR 19 0 MCU DATA W WEN WRITE addr V1 addr V1 addr V2 XX addr V2 XX addr Vx XX addr Vy XX addr Vz XX XX addr Vy X Write Write Write addr V1 2 Word CLK Halfword Halfword S3 S4 R W Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 69: ... V1 CS S1 W W OE EB 0 1 DATA 15 0 MCU TA addr Vx addr V2 CS1 CS2 XX addr Vy XX S3 S1 S2 addr V2 XX W S3 S1 addr Vz XX addr Vw XX S2 W OE EB EB ADDR 19 0 MCU DATA X W W READ WRITE READ WSC 2 EDC 0 WRITE WSC 1 WWS 0 XX XX XX CLK W W R R W WEN OEA S2 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 70: ...dr V1 CS S1 W W OE EB 0 1 DATA 15 0 MCU TA addr Vx addr Vy CS1 CS2 XX addr Vy XX S1 S2 addr V2 XX W S3 S1 addr Vz XX addr Vw XX S2 W S2 OE EB EB ADDR 19 0 MCU DATA X S3 R W R W READ WSC 1 EDC 1 WRITE WSC 1 WWS 0 XX XX CLK S4 W IDLE WEN R W OEA XX Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 71: ...WSC 5 MCU ADDR MCU R W MCU TREQ CS R W DATA 7 0 MCU TA A0 MCU DATA S1 S2 W1 W2 W1a W2a W3 W3a W4 W4a Addr x XXXXXXXXXXX READ CLK S1 W5 S3 W5a S4 S2 R Addr x Addr y OE EB 0 1 Addr y IDLE OEA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 72: ...s CSA 1 WSC 5 MCU ADDR MCU R W MCU TREQ CS EB 0 1 DATA 7 0 MCU TA ADDR0 MCU DATA S1 S2 W1 W2 W1a W2a W3 W3a W4 W4a Addr x CLK S2 W5 S3 W5a S4 S1 Addr x W W Addr y Addr y R W WEN IDLE Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 73: ...WS 0 MCU ADDR MCU R W addr V1 MCU TREQ addr V1 S1 OE EB 0 1 DATA 15 0 MCU TA addr V2 CS2 CS2 addr V2 XX S1 S2 S1 addr Vy XX S2 S2 OE EB EB ADDR 19 0 MCU DATA X Read Write READ WRITE XX CLK CS Read Write R W X Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 74: ...wing different parts of the same peripheral to use different frequencies imply rigid constraints on clock frequencies and synchronization issues which must be addressed carefully Refer to each peripheral definition for further details In addition the CLKOUT pin can be driven by one of the internal clock sources LOW_REFCLK or HI_REFCLK under software control The following table describes the clock ...

Page 75: ...CLK receiver and buffer CLKOUT circuitry Control circuitry for generation and gating of high frequency clocks to the CPU and peripherals Divider circuits for generation of low frequency clocks for peripherals A diagram of the clock module is shown in Figure 8 1 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 76: ...68 kHz R 4 8 192 kHz R 32 256 Hz POR PIT_RUNNING 8 192 kHz PIT_CLK TOD_CLK KPP_CLK CKO selector CKOE CKOS CLKOUT CLKIN STBY STBY STOP DOZE WAIT R 128 2 Hz WDOG_CLK to CPU EIM Interrupt Controller STBY STOP CLKIN input buffer is a special low signal swing receiver RB RS X1 C1 C2 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 77: ...s which con tinue to run and have the capability of producing interrupts may cause the CPU to exit the doze mode and return to the run mode Peripherals which were stopped will restart operation on exit from doze mode as defined for each peripheral 8 2 1 4 Stop Mode Stop mode affects the CPU in the same manner as wait but with a different code on the CPU LPMD output signals which are monitored by p...

Page 78: ...tion The state machine is reset and the shift register is cleared It is assumed that when stop mode is initiated there is some other method of shutting down external devices Dur ing the stop mode the ISPI clocks are shut down Coming out of stop mode returns the ISPI to an idle mode To avoid erroneous operation ensure that the ISPI is in an idle state before entering the stop mode 8 2 2 3 PWM In do...

Page 79: ...for its reference clock and does not stop in any of the low power modes 8 2 2 8 Keypad Port The keypad port module uses the CPU_CLK for its internal operation only for CPU accesses thus the module is not affected by the low power modes and is capable of waking up the CPU from all low power modes unless it is explicitly disabled A pres caled version of LOW_REFCLK is used for the debounce logic and ...

Page 80: ...le CKOE bit in the reset timer block Table 8 2 CPU Core and Peripherals in Low Power Modes Module Peripheral Clock Status during Mode Wake up Capability Run Wait Doze Stop Standby CPU Core Running Stopped Stopped Stopped Stopped UART Running Running Yes Prog Yes Stopped No Stopped No ISPI Running Running Yes Prog Yes Stopped No Stopped No Interrupt Controller Running Stopped Yes Stopped Yes Stoppe...

Page 81: ...MOTOROLA CLOCK MODULE AND LOW POWER MODES MMC2001 8 8 REFERENCE MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 82: ...s Register TODCSR Supervisor Only 10001008 Time of Day Seconds Register TODSR Supervisor Only 1000100C Time of Day Fraction Register TODFR Supervisor Only 10001010 Time of Day Seconds Alarm Register TODSAR Supervisor Only 10001014 Time of Day Fraction Alarm Register TODFAR Supervisor Only 10001018 Reserved Supervisor Only 1000101C Watchdog Control Register WCR Supervisor Only 10001020 Watchdog Ser...

Page 83: ...low when either qualified external resets are detected or on chip resets watchdog timer power up reset circuitry are generated The minimum length is eight LOW_REFCLK cycles The RSTOUT pin remains low if either reset input pin is held low 9 3 2 Reset Sources Three sources are capable of generating a reset condition An external qualified low condition on either reset input pin The RSTIN signal must ...

Page 84: ...EFCLK cycles before the RSTOUT pin is negated and this state is used to control the first memory access for the initial program counter value The memory access is from either the internal ROM or external memory connected to CS0 9 3 4 Reset Source Chip Configuration Register RSCR This status and control register gives the state of the reset sources and serves to control the CLKOUT pin Writes to thi...

Page 85: ... chip It is not affected by the other reset sources It is cleared by writing to RSCR WDR Watchdog Reset This bit is set when the watchdog timer expires It is cleared by POR a qualified assertion of the RSTIN pin a qualified assertion of the LVRSTIN pin or by writing to RSCR 9 4 Time of Day Timer The time of day timer TOD is a free running timer that is clocked by the crystal oscil lator at a frequ...

Page 86: ... is temporarily disabled after a write to the TODSAR until the TODFAR is written This prevents an alarm match from occurring before the entire 40 bit alarm value is written The TOD fraction and seconds counters are undefined after a POR operation and are unaffected by any other reset source The TOD alarm is disabled by any reset source 9 4 2 TOD in Low Power Modes The TOD is unaffected by the low ...

Page 87: ...he watchdog reset or by a reset initiated by the external reset signal but is undefined after a POR Access this register with 32 bit loads and stores only Figure 9 5 TOD Seconds Register 9 4 5 TOD Fraction Register TODFR The 32 bit time of day fraction register holds eight bits of data that represent the binary fraction of a second It is clocked by the 32 768 kHz LOW_REFCLK divided by 128 256 Hz R...

Page 88: ...onds Alarm Register 9 4 7 TOD Fraction Alarm Register TODFAR The time of day fraction alarm register is a 32 bit read write register which holds eight bits of data to be compared to the TOD fraction register The comparison is made every 1 256 of a second if the alarm function is enabled by the AE bit in the TODCSR This register is not affected by any of the reset conditions Access this register wi...

Page 89: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R TOD FRACTION ALARM REGISTER 0 0 0 0 0 0 0 0 W RESET Undefined on POR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET From Clock Block Reset WDE one time write DBUG from CPU WDBG one time write Watchdog Control Register WCR 6 Bit Counter Underflow Watchdog Service Register WSR WSTP WDBG WDE STOP from CPU WSTP one time...

Page 90: ...tware it cannot be disabled The watchdog enable bit WDE is located in the watchdog control regis ter At reset the watchdog control register and watchdog service register are initial ized to zero 9 5 3 Watchdog Timer Service Operation A service sequence must be executed periodically to keep the watchdog from timing out and causing a reset The service routine is based on writing to the watchdog ser ...

Page 91: ...the watchdog in different modes of operation The write once bits can only be written once after a reset condi tion Subsequent attempts to write to them will not affect the data previously written Access this register with 32 bit loads and stores only Figure 9 10 Watchdog Control Register WT Watchdog Time Out The six bit WT field contains the time out value These bits are reloaded into the watchdog...

Page 92: ... by 0xAAAA before the selected rate expires the watchdog sets the WDR bit in the reset source register and asserts a system reset Both writes must occur in the order listed prior to the time out but any number of instructions can be executed between the two writes Access this register with 32 bit loads and stores only Figure 9 11 Watchdog Service Register 9 6 Interval Timer PIT The interval timer ...

Page 93: ...U core which runs from the CPU_CLK clock synchronization logic is required internal to the PIT This logic requires that the CPU clock frequency driven from HI_REFCLK be greater than or equal to the LOW_REFCLK clock that the counter clocks are derived from Figure 9 13 Starting a Count from an Off State 9 6 2 PIT as a Set and Forget Timer This mode of operation is selected when the RLD bit in the PI...

Page 94: ...ounter rolls over from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to count When the counter reaches a count of zero the PIT interrupt flag ITIF is set in the ITCSR If the PIT interrupt enable ITIE bit is set in the ITCSR the interrupt flag can issue an interrupt to the CPU The counter may by directly initialized without having to wait for the count to reach zero when t...

Page 95: ...the modulus latch is written 0 Modulus latch is a holding register for values to be loaded into the counter when the count expires to zero 1 Modulus latch is transparent All writes to the latch will also overwrite the counter contents ITIE PIT Interrupt Enable This bit controls the PIT interrupt function 0 ITIF is inhibited from reaching the CPU 1 ITIF is allowed to request an interrupt ITIF PIT I...

Page 96: ... subsequent reloads until changed by another write to ITDR This value is initialized to the maximum count of 0xFFFF on reset On a read the ITDR returns the value written in the modulus latch The only way to change the value of the count directly is to preload a modulus with the OVW bit set to one The counter value can be read from the PIT alternate data register Access this register with 32 bit lo...

Page 97: ...ed in the respective mode When doze or stop mode is exited timer operation reverts to what it was prior to entering doze or stop mode 9 6 9 PIT in Debug Mode In debug mode the module may either continue to run or be halted If the DBG bit is set in the PIT control status register the timer is halted When debug mode is exited the timer operation reverts to what it was prior to entering debug mode IT...

Page 98: ...interrupt enable register NIER allows individual bit masking of the INTSRC register and a normal interrupt pending register NIPND indicates pending normal interrupt requests A logical AND is performed on the INTSRC register and the content of the NIER register to form the content of the nor mal interrupt pending NIPND register A logical bit wise OR is performed on all the NIPND register bits to fo...

Page 99: ...Interrupt Controller Programming Model Control and status registers for the interrupt controller begin at address 0x40002000 10 2 1 Interrupt Source Register INTSRC Access the 32 bit interrupt source register with 32 bit loads only Figure 10 1 Interrupt Source Register Table 10 1 Interrupt Controller Address Map Address Use Access 10000000 Interrupt Source Register INTSRC Supervisor Only 10000004 ...

Page 100: ... causes that interrupt to become pending and a request to the CPU is asserted if not already outstanding 10 2 3 Fast Interrupt Enable Register FIER Access the 32 bit fast interrupt enable register with 32 bit loads and stores only Figure 10 3 Fast Interrupt Enable Register NIER Normal Interrupt Enable Register 10000004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN31 EN30 EN29 EN28 EN27 EN26 E...

Page 101: ...g Flag x This bit indicates a pending normal interrupt request from the corresponding interrupt source 0 No request 1 Interrupt request pending When a normal interrupt enable flag is set and the corresponding interrupt line is asserted the interrupt controller asserts a normal interrupt request The normal inter rupt pending flags reflect the interrupt input lines which are asserted and are current...

Page 102: ...nput The fast interrupt pending flags reflect the interrupt input lines which are currently enabled to generate a fast interrupt and are asserted 10 2 6 Interrupt Request Input Assignments The assignment of bits within the interrupt registers to interrupt sources is shown in Table 10 2 FIPND Fast Interrupt Pending Register 10000010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FP31 FP30 FP29 FP2...

Page 103: ...rol 7 Time of day alarm 8 PIT 9 Unused 10 PWM0 11 PWM1 12 PWM2 13 PWM3 14 PWM4 15 PWM5 16 UART0 transmit 17 UART1 transmit 18 UART0 receive 19 UART1 receive 20 ISPI 21 INT0 22 INT1 23 INT2 24 INT3 25 INT4 26 INT5 27 INT6 28 INT7 29 Unused 30 Unused 31 Unused Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 104: ...key features of the UART channels are Full duplex operation Direct support of Infrared Data Association mechanism Robust receiver data sampling with noise filtering 16 entry FIFOs for transmit and receive 7 or 8 bit operation with optional even or odd parity and one or two stop bits Generation and detection of break 16x bit clock generator for bit rates of 300 bps to 115 2 Kbps Three maskable inte...

Page 105: ...ower state Interrupts are enabled by the RTSD EN bit in UART control register 1 This pin can also be used as a general purpose input whose status is read in the RTSS bit in the UART status register 11 2 2 CTS Clear to Send UART0 The UART signals an external device that it is ready to receive data by asserting the CTS output If the receiver detects a pending overrun it negates the CTS output This p...

Page 106: ...urpose I O pin when the UART RXD function is not being used 11 3 Sub Block Description The UART contains four sub modules This section briefly describes the basic func tionality of the four blocks 11 3 1 Transmitter The transmitter accepts a parallel character from the CPU and transmits it serially The start stop and parity if enabled bits are added to the character The transmitter posts a maskabl...

Page 107: ...ta a narrow pulse is expected for each zero transmit ted and no pulse is expected for each one transmitted Circuitry external to the IC transforms the infrared signal to an electrical signal 11 3 4 16x Bit Clock Generator The 16x bit clock generator provides the pre scaled bit clocks to the transmitter and receiver blocks A divide ratio from one to 4096 may be selected in the UBRGR regis ter The 1...

Page 108: ...rror An error condition in which the calculated parity of the received data bits in the frame is different from the parity bit received on the RXD line Parity error is only calculated after an entire frame is received Overrun Error An error condition in which the latest character received is ignored to prevent overwriting an already existing character in the UART receiver FIFO An overrun error ind...

Page 109: ...Register U0PDR Supervisor Only 10009090 to 10009FFF Reserved Supervisor Only UART1 1000A000 UART1 Receive Register U1RX Supervisor Only 1000A002 Not Used Supervisor Only 1000A004 to 1000A03E U1RX Echoes On Word Boundaries Supervisor Only 1000A040 UART1 Transmit Register U1TX Supervisor Only 1000A042 Reserved Supervisor Only 1000A044 to 1000A07E U1TX Echoes On Word Boundaries Supervisor Only 1000A0...

Page 110: ...ndicates that the character present in the RX DATA field has an error status The error can be an OVRRUN FRMERR BRK or PRERR This bit is updated and valid for each received character 0 No error status detected 1 Error status detected At reset this bit is cleared to zero OVRRUN Receiver Overrun When set this read only bit indicates that the receiver ignored data to prevent over writing the data in t...

Page 111: ...o be set when this bit is set This bit is valid for each character read from the FIFO 0 Character is not a break character 1 Character is a break character At reset this bit is cleared to zero PRERR Parity Error When set this read only bit indicates that the current character was detected with a parity error The data is possibly corrupted This bit is updated for each character read from the FIFO W...

Page 112: ...generated by the transmitter A maskable interrupt is generated whenever the data level in the TX FIFO drops below the selected threshold The bits are encoded as follows At reset these bits are cleared to zero U0TX UART0 Transmitter Register 10009040 U1TX UART1 Transmitter Register 1000A040 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 TX DATA RESET 0 0 0 0 0 0 0 0 X X X X X X X X U0CR1 UAR...

Page 113: ...erated by the receiver A maskable interrupt will be generated whenever the data level in the RX FIFO reaches the selected threshold At reset these bits are cleared to zero RRDYEN Receiver Ready Interrupt Enable Setting this bit enables an interrupt when the receiver has data in the RX FIFO The fill level in the RX FIFO at which an interrupt is generated is controlled by the RxFL bits Clearing this...

Page 114: ...ters remaining will be transmit ted when the break is terminated This bit cannot be changed until the UART EN and TX EN bits in the UART control register 1 CR1 are set 0 Do not send break 1 Send break continuous zeros At reset this bit is cleared to zero DOZE Doze Mode When the CPU executes a doze instruction and the system is placed in the doze mode the DOZE bit affects operation of the UART If t...

Page 115: ...eset since this bit is cleared to zero the CTS pin is controlled by the CTS bit which is also cleared to zero on reset This means that on reset the CTS signal is negated 0 CTS pin controlled by the CTS bit 1 CTS pin controlled by the receiver At reset this bit is cleared to zero CTS CTS bit This bit controls the CTS pin while the CTSC bit is negated While CTSC is asserted this bit has no function ...

Page 116: ...bit mode The transmitter then ignores B7 and the receiver sets B7 to zero This bit can be changed between transmissions or recep tions If it is changed while a transmission or reception is in progress however the length of the current character being transmitted or received is unpredictable 0 7 bit transmit and receive character length 1 8 bit transmit and receive character length At reset this bi...

Page 117: ... indicates that the TX FIFO has emptied below its target threshold and needs data This bit is automatically cleared when the data level in the TX FIFO goes beyond the set threshold level 0 Transmitter does not need data 1 Transmitter needs data interrupt posted At reset this bit is set to one RRDY Receiver Ready Interrupt Flag When set this bit indicates that the receive FIFO data level is above t...

Page 118: ...red to zero LOOP Loop TX and RX for Test This bit controls loopback for test purposes While this bit is high the receiver input is internally connected to the transmitter and ignores the RxD pin The transmitter is unaffected by this bit This loopback operates to connect the data on the TxD pin directly to the voting logic If infrared mode is enabled IR_EN is active the effect of activating this bi...

Page 119: ...ese bits are cleared to zero 11 5 2 UART Data Direction Register UDDR The read write UART data direction register controls the direction of UART GPIO pins Figure 11 10 UART Data Direction Register Table 11 4 UART Pins GPIO Assignment GPIO Bit UART Pin P0 RXD P1 TXD P2 RTS P3 CTS U0PCR UART0 Port Control Register 1000908A U1PCR UART1 Port Control Register 1000A08A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 120: ...o configure the missing pins as general purpose outputs 11 6 Data Sampling Technique on the Receiver The UART receiver is responsible for synchronization to the serial data stream and recovery of data characters Since the data stream has no clock data recovery depends on the transmitting device and the receiving device operating at close to the same bit rate The UART system can tolerate a moderate...

Page 121: ...d the RT clock is reset to state RT1 after each sample Once the qualifiers are found the beginning of a start bit is tentatively assumed and successive samples are assigned successive RT state numbers The next six sam ples are taken as start bit verification samples If even one of these is a logic one the low at RT1 is assumed to have been noise and the asynchronous search is started again When th...

Page 122: ...rify that this bit time is indeed the start bit The samples at RT8 RT9 and RT10 or RT9 RT10 and RT11 are called the data sam ples 4 These samples drive a majority voting circuit to determine the logic sense of the bit time In this ideal case the actual start bit and the perceived start bit match The resolution of the RT clock leads to an uncertainty about the exact placement of the leading edge of...

Page 123: ...e is rejected and the search is restarted When the sample at the actual beginning of the start bit is detected the preceding three samples are ones the start bit is now perceived to begin here In this case the three samples taken at RT2 RT3 RT4 RT5 RT6 and RT7 3 now verify that the start bit has been found If the noise bit 1 is further away from the beginning of the actual start bit the perceived ...

Page 124: ...re are no more cases of four logic ones in a row 3 the start bit is never detected Because the circuit could not locate the start bit the frame will be received as a framing error improperly received or missed entirely depending on the data in the frame and when the start logic synchronized on what it thought was a start bit This causes incorrect data reception RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 ...

Page 125: ...e data samples to be erroneously detected as logic ones This is rejected therefore as a start bit because the majority of samples RT8 RT9 and RT10 3 suggest it should be a logic one RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT4 RT5 RT6 RT7 RT8 RT9 RT3 RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 RXD Pin Samples RT CLK 16X Bit Rate RT CLK State Reset RT Actual Star...

Page 126: ...taken the right decision 11 7 UART Operation in Low Power System Modes The UART serial interface operates as long as the 16x bit clock generator is provided with the system clock The peripheral interface is operational while the CPU_CLK is running The three bits RXEN TXEN and UART EN set by the user give the capabil ity to control low power modes through software Table 11 5 shows UART functional i...

Page 127: ...cter and signal to the far end transmitter or receiver to stop sending or receiving There is no guarantee that the data currently present in the receiver and transmitter FIFOs will not be corrupted 11 8 UART Operation in System Debug Mode In debug mode reads of the UART receiver register do not cause the RX FIFO to bump That is the value at the read side of the RX FIFO does not change as a result ...

Page 128: ...er a serial link Enable and clock signals are used to exchange data between the two devices If the external device is a transmit only device e g an A D converter the ISPI output port can be ignored or used for other purposes Figure 12 1 shows a block diagram of the ISPI Figure 12 1 ISPI Channel Block Diagram 12 2 Operation The ISPI provides three operating modes Manual mode is a traditional SPI ma...

Page 129: ...ces on the market 12 2 1 Manual Master Mode When a data exchange is needed the user sets the SPI_EN bit in the ISPI control register Control values such as the number of transfer clocks polarity and phase are also loaded into the ISPI control register The transfer is initiated by writing the ISPI Tx data register During the transfer data in the shift register is exchanged with data in the peripher...

Page 130: ...nterval_Count 2 HI_REFCLK_Period Baud_Count Clock_Count 1 12 2 3 Slave Mode In slave mode data exchanges are controlled by external devices through the pins SPI_CLK and SPI_EN If pin SPI_EN is enabled low then data is latched into the shift register on every other edge of SPI_CLK the latching edge is determined by the POL and PHA bits in the ISPI control register Data is transferred from the shift...

Page 131: ... is enabled a selectable number of clock pulses are issued In slave mode this pin is an input but controls SPI operation just as it does in the two master modes In slave mode SPI_CLK must not exceed HI_REFCLK 16 12 3 5 SPI_GP This output pin is a general purpose output which can be used as a control signal to a selected external device The value driven out is controlled by the SPIGP bit in the ISP...

Page 132: ...ified relative to the CLOCK COUNT field in the ISPI control register For example if the exchange length is ten bits CLOCK COUNT 0x9 the MSB of the outgoing data is bit nine The first bit presented to the external device is bit 9 followed by the remaining nine less signifi cant bits 12 4 2 ISPI Control Register The ISPI control register SPCR along with the ISPI interval control register controls th...

Page 133: ...ense of the SPI_EN pin relative to the SPI_EN register bit in the ISPI control register This is required because in interval mode the state machine must assert and then negate the SPI_EN pin The SNS bit has an effect only when the SPI_EN pin is an output If the SPI_EN pin is an input then it is active low and the SNS bit has no effect 0 SPI_EN pin is active low 1 SPI_EN pin is active high DRV Driv...

Page 134: ... rate of the ISPI bit clock based on divisions of the system clock The master clock for the ISPI is HI_REFCLK CLOCK COUNT These bits select the length of the transfer and control the justification of data From two to 16 bits can be transferred A count of all zeros causes the ISPI to be disabled Table 12 2 BAUD RATE Field Settings Value Divide By 000 8 001 16 010 32 011 64 100 128 101 256 110 512 1...

Page 135: ...SPI is operating in slave mode and this bit is ignored 0 ISPI is not operating in interval mode 1 ISPI is operating in interval mode if MSTR 1 INTERVAL COUNT In interval mode this register value is loaded into the ISPI interval timer upon comple tion of a transfer Each bit clock period the value in this counter is decremented by one When the value in the register reaches zero then XCH is set and a...

Page 136: ...achine is performing a transfer In manual mode XCH is set by writing the ISPI data register In interval mode XCH is set auto matically by the interval timer In slave mode XCH is set when pin SPI_EN is asserted and is negated briefly once the counters determine the completion of a transfer It is then reasserted if SPI_EN is still asserted In all modes XCH is reset upon completion of a transfer 0 SP...

Page 137: ...ster SPDR to 0x0013 SPCR is programmed differently from the manual mode example because SPI_EN SNS and BAUD RATE are ignored in slave mode MSTR has to be cleared to enable slave mode 12 5 3 Interval Model Example With a 16 38 MHz clock HI_REFCLK 61 ns To program the ISPI to transfer 10 bit words at 8 kHz intervals 1 Program clock count to 0x9 2 Program baud rate to 0x3 divide HI_REFCLK by 64 3 Set...

Page 138: ...e middle it is assumed that when stop is initiated there is some other method of shutting down external devices The SPDR value is retained so that the transfer can be re initiated after the system is restarted by simply writing the SPI control register 12 7 ISPI Operation in System Debug Mode In debug mode the only modification to ISPI behavior is that the clear on access function of the IRQ bit i...

Page 139: ...MOTOROLA INTERVAL MODE SERIAL PERIPHERAL INTERFACE MMC2001 12 12 REFERENCE MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 140: ...triggered triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal However as the fall time of the interrupt signal increases the probability of generating multiple interrupts due to this noise also increases All default to general purpose input pins at reset The interrupt request function on these pins is masked in the interrupt controller fast int...

Page 141: ...2 Edge Port Pin Assignment Register EPPAx Edge Port Pin Assignment Select Field x Pins configured as level sensitive are inverted so that a logic low on the external pin represents a valid interrupt request Level sensitive interrupt inputs are not latched To guarantee that a level sensitive interrupt request is acknowledged the interrupt source must keep the signal asserted until acknowledged by s...

Page 142: ... of the port is configured as an output the data stored for that bit is driven onto the pin Reads of this register return the value sensed on the pins for those pins configured as inputs or the data stored in the register for the pins configured as outputs X Unaffected by reset Figure 13 4 Edge Port Data Register Table 13 2 EPPAx Field Settings Value Meaning 00 Pin INTx defined as level sensitive ...

Page 143: ...il cleared by writing it to a one Pin transitions do not affect this register if the pin is configured as level sensitive EPPARx 00 The corresponding flag bit s are cleared to zero in this case When a pin is configured as a general purpose output writes to EPDR that cause the selected level or edge inter rupt will set the corresponding bit in EPFR The outputs of this register drive the cor respond...

Page 144: ...P is shown in Figure 14 1 Figure 14 1 KPP Block Diagram KPDR 15 8 KDDR 15 8 KPDR 7 0 Keypad Matrix Up to 8 x 8 KPCR 15 8 KDDR 7 0 Debounce Chain KPSR To Interrupt Controller KPCR 7 0 256 Hz Pad Drivers Row Enable Data Direction KDDR and Open Drain Enable KPCR Controls Pull up Data Direction Controls KDDR Controls KPCR Freescale Semiconductor I Freescale Semiconductor Inc For More Information On Th...

Page 145: ...g the eight most significant bits KDDR 15 8 can be designated as open drain outputs by writing a one into the appropriate bits in KPCR The pins representing the lower eight bits KDDR 7 0 are always totem pole style drive when configured as outputs 14 3 KPP Programming Model 14 3 1 Keypad Control Register KPCR The keypad control register KPCR determines which of the eight possible column strobes ar...

Page 146: ...uded in keypad key press detect 14 3 2 Keypad Status Register KPSR The keypad status register KPSR reflects the state of the keypress detect circuit The keypad key depress KPKD status bit is set when one or more enabled rows are detected low after synchronization The KPKD status bit remains set until cleared by software The KPKD bit may be used to generate a maskable key depress interrupt If desir...

Page 147: ...E Key Release Interrupt Enable 0 No interrupt request is generated when KPKR is set 1 An interrupt request is generated when KPKR is set KDIE Key Depress Interrupt Enable 0 No interrupt request is generated when KPKD is set 1 An interrupt request is generated when KPKD is set KRSS Key Release Synchronizer Set The key release synchronizer is set by writing a logic one into this bit Reads return a v...

Page 148: ... pin is configured as output 14 3 4 Keypad Data Register KPDR The 16 bit keypad data register is used to access the column and row data Data writ ten to this register is stored in an internal latch and for each pin configured as an out put the stored data is driven onto the pin A read of this register returns the value on the pin for those bits configured as inputs Otherwise the value read is the ...

Page 149: ... as inputs On chip pull up resistors are implemented for active keypad rows as defined in SECTION 4 SIGNAL DESCRIPTIONS Row inputs must also be enabled in the keypad control register to be active in the interrupt generation circuit Discrete switches that are not part of the matrix may be connected to any unused row inputs The second terminal of the discrete switch is connected to ground The hard w...

Page 150: ... when scanning to prevent a possible DC path between power and ground through two or more switches 14 4 5 Glitch Suppression on Keypad Inputs A glitch suppression circuit qualifies the keypad inputs to prevent noise from inadvert ently interrupting the CPU The circuit is a four state synchronizer clocked from a 256 Hz clock source This clock must continue to run in any low power mode for which the...

Page 151: ...re 14 7 three keys pressed simultaneously can short between the column currently scanned by software and another column Depending on the location of the third key pressed a ghost key press may be detected Keypad 256 Hz Matrix FF D Q FF D Q FF D Q FF D Q S R Clear KPKD Status Flag NAND R R R R KPKD FF D Q FF D Q FF D Q FF D Q S R S S S S KPKR Clear KPKR Status Flag Clear KPKD Synchronizer Set KPKR ...

Page 152: ...gin keypad scanning routine a Disable keypad interrupts b Write ones to KPDR 15 8 setting column data to ones c Configure columns as totem pole outputs d Configure columns as open drain e Write a single column to zero and write others to one f Sample row inputs and save data Multiple key presses can be detected on a single column g Repeat steps b to f for remaining columns h Return all columns to ...

Page 153: ...set the KPKR synchronizer chain clear the KPKD synchronizer chain j Re enable the appropriate keypad interrupt s KDIE to detect a key hold condition or KRIE to detect a key release event Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 154: ...lter the PWM channel can be used as a digital to analog converter Figure 15 1 is a block diagram of a single PWM channel Figure 15 1 PWM Block Diagram By feeding a stream of sample values to the PWM into the width register and provid ing a low pass filter on the output the output pin can provide a digitally generated sound source The reconstruction rate is determined by the selected period Typical...

Page 155: ... channel can independently select a prescaler tap point In addition each channel provides a maskable interrupt request that can be asserted after each period compare event Channels can be used as periodic interrupt sources In this case the output pin asso ciated with a channel can be used as a general purpose I O pin operating indepen dently of the timing function 15 2 PWM Programming Model This s...

Page 156: ...er Register PWMCTR2 Supervisor Only 10005018 PWM3 Control Register PWMCR3 Supervisor Only 1000501A PWM3 Period Register PWMPR3 Supervisor Only 1000501C PWM3 Width Register PWMWR3 Supervisor Only 1000501E PWM3 Counter Register PWMCTR3 Supervisor Only 10005020 PWM4 Control Register PWMCR4 Supervisor Only 10005022 PWM4 Period Register PWMPR4 Supervisor Only 10005024 PWM4 Width Register PWMWR4 Supervi...

Page 157: ...post a PWM interrupt immediately for debugging purposes This bit is cleared automatically after it is read while set If IRQ EN is cleared this bit will not be set 0 No interrupt posted 1 PWM period rolled over IRQ EN Interrupt Request Enable This bit controls PWM interrupt generation While this bit is low the interrupt is dis abled 0 PWM interrupt disabled 1 PWM interrupt enabled LOAD Load PWMPR a...

Page 158: ...being used as a GPIO pin 0 Normal PWM polarity 1 Inverted PWM polarity MODE PWM Mode This bit selects whether the PWM pin is used for GPIO or for the PWM function 0 General purpose I O mode 1 PWM mode COUNT EN Counter Enable This bit enables or disables the PWM counter The counter is actually enabled or dis abled some time after the CPU writes this bit It is enabled on the next rising PCLK edge fo...

Page 159: ... another period Figure 15 5 PWM Period Registers PERIOD Pulse Period This is the value that causes the counter to be reset There is one special case When PERIOD 0 the output is never set high 0 duty cycle In this case the compara tor is loaded and the counter reset on every PCLK In addition if enabled an interrupt request is generated on every PCLK Table 15 2 CLK SEL Field Settings Value Divide By...

Page 160: ...thout disturbing the counter Figure 15 7 PWM Count Registers COUNT Count Value This is the current count value PWMWR0 PWM0 Width Register 10005004 PWMWR1 PWM1 Width Register 1000500C PWMWR2 PWM2 Width Register 10005014 PWMWR3 PWM3 Width Register 1000501C PWMWR4 PWM4 Width Register 10005024 PWMWR5 PWM5 Width Register 1000502C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 WIDTH W RESET 0 0 0 0...

Page 161: ...current period In stop mode the PWM halts immediately due to halting of system clocks and forgets the state of any period the state machine is reset and the shift register is cleared It is assumed that when stop is initiated the channels have been disabled Table 15 3 PWM Range at 16 MHz Divide By Approximate Period Range at 16 MHz Resolution at 16 MHz 4 0 5 µs 256 µs 25 µs 8 1 µs 512 µs 5 µs 16 2 ...

Page 162: ...controller and its resources is based on the TAP defined for JTAG in the IEEE 1149 1a 1993 standard 16 2 Operation An instruction is scanned into the OnCE module through the serial interface and then decoded Data may then be scanned in and used to update a register or resource on a write to the resource or data associated with a resource may be scanned out for a read of the resource PSTAT ATTR ADD...

Page 163: ...ctions and data into and out of the CPU scan chain Required data is accessed by executing the scanned instructions Memory locations may be read by scanning in a load instruction to the CPU that references the desired memory location executing the load instruction and then scanning out the result of the load Other resources are accessed in a similar manner Figure 16 2 OnCE Controller Capture DR Shi...

Page 164: ...st DBGRQ to the CPU This causes the CPU to finish the instruction being executed save the instruction pipeline information enter debug mode and wait for further com mands Asserting DBGRQ causes the device to exit stop doze or wait mode 16 3 1 Debug Serial Input TDI Data and commands are provided to the OnCE controller through the TDI pin Data is latched on the rising edge of the TCK serial clock D...

Page 165: ...ing executed save the instruction pipeline information enter debug mode and wait for commands to be entered from the TDI line If DE was used to enter debug mode then DE must be negated after the OnCE responds with an acknowledgment and before sending the first OnCE command The assertion of this pin by the CPU acknowledges that it has entered debug mode and is waiting for commands to be entered fro...

Page 166: ... to the control function provided by the DR control bit in the OnCE control register OCR This input is maskable by a control bit in OCR 16 5 2 CPU Debug Request DBGRQ The DBGRQ signal is asserted by the OnCE control logic to request the CPU to enter the debug state It may be asserted for a number of different conditions Assertion of this signal causes the CPU to finish the current instruction bein...

Page 167: ... Control Register OCR OnCE Status Register OSR All OnCE registers are addressed by means of the RS field in the OMCR as shown in Table 16 1 Other OnCE registers are described in 16 8 Memory Breakpoint Logic and 16 9 OnCE Trace Logic 16 6 1 OnCE Command Register OCMR The OnCE command register OCMR is an 8 bit shift register that receives its serial data from the TDI pin This register corresponds to...

Page 168: ...er selected Otherwise the GO bit is ignored The pro cessor leaves debug mode after the TAP controller update DR state is entered 0 Inactive no action taken 1 Execute instruction in IR EX Exit Command When the EX bit is set the processor leaves debug mode and resumes normal oper ation until another debug request is generated The exit command is executed only if the Go command is issued and the oper...

Page 169: ... Base Register B BABB 01001 Breakpoint Address Mask Register A BAMA 01010 Breakpoint Address Mask Register B BAMB 01011 CPU Scan Register CPUSCR 01100 No Register Selected Bypass 01101 OnCE Control Register OCR 01110 OnCE Status Register OSR 01111 Reserved Factory Test Control Register do not access 10000 Reserved MEM_BIST do not access 10001 10110 Reserved Bypass do not access 10111 Reserved LSRL...

Page 170: ...l Control Field Settings SQC 1 0 Meaning 00 Disable sequential control operation Memory breakpoints and trace operation are unaf fected by this field 01 Suspend normal trace counter operation until a breakpoint condition occurs for memory breakpoint B If this mode is selected memory breakpoint B occurrences no longer cause a breakpoint request to be generated Instead trace counter comparisons are ...

Page 171: ...ce accesses These bits are cleared on test logic reset See Table 16 3 for the definition of the BCA and BCB fields Table 16 3 Memory Breakpoint Control Field Settings BC4 BC3 BC2 BC1 BC0 Description 0 0 0 0 0 Breakpoint disabled 0 0 0 0 1 Qualify match with any access 0 0 0 1 0 Qualify match with any instruction access 0 0 0 1 1 Qualify match with any data access 0 0 1 0 0 Qualify match with any c...

Page 172: ...et due to the CPU entering debug mode for another reason This bit is cleared on test logic reset or when debug mode is exited with the GO and EX bits set SWO Software Debug Occurrence This read only status bit is set when the processor enters debug mode of operation as a result of the execution of the bkpt instruction This bit is cleared on test logic reset or when debug mode is exited with the GO...

Page 173: ...ddress range The breakpoint logic contains an input latch for addresses registers that store the base address and address mask comparators attribute qual ifiers and a breakpoint counter Figure 16 7 illustrates the basic functionality of the OnCE memory breakpoint logic This logic is duplicated to provide two independent breakpoint resources Address comparators can be used to determine where a prog...

Page 174: ...on is used to decrement the breakpoint counter conditionally if its contents are non zero If the contents are zero the counter is not decremented and the breakpoint event occurs ISBKPTx asserted 16 8 1 Memory Address Latch MAL The memory address latch MAL is a 32 bit register that latches the address bus on every access ADDR 31 0 ATTR Address Base Register x Address Comparator DSI DSO DSCK MATCH B...

Page 175: ...ccur before a memory breakpoint is declared The memory access event is specified by the RCx and BCx 4 0 bits in the OCR register and by the memory base and mask registers On each occurrence of the memory access event the breakpoint counter if currently non zero is decremented When the counter has reached the value of zero and a new occurrence takes place the ISBKPTx signal is asserted and causes t...

Page 176: ...counter is cleared by hardware reset 16 9 2 Trace Operation The following steps initiate trace mode operation 1 Load the counter with a value This value must be non zero unless the sequential breakpoint control capability described in 16 6 2 OnCE Control Register OCR is being used In this case a value of zero indicating a single instruction is allowed 2 Initialize the program counter and instructi...

Page 177: ...ent instruction and then enter debug mode Note that in this case the device completes the execution of the current instruction and stops after the newly fetched instruction enters the CPU instruction latch This process is the same for any newly fetched instruction including instructions fetched by interrupt pro cessing or those that will be aborted by interrupt processing 16 10 3 Debug Request Dur...

Page 178: ...the break point is acknowledged after the completion of the memory access instruction 16 11 Pipeline Information and Write Back Bus Register A number of on chip registers store the CPU pipeline status and are configured in a single scan chain for access by the OnCE controller The CPUSCR OnCE register contains these processor resources which are used to restore the pipeline and resume normal device...

Page 179: ...cessing is to be resumed the IR can be loaded with the value originally scanned out 16 11 3 Control State Register CTL The control state register CTL is used to set control values when debug mode is exited On scan in this register is used to control specific aspects of the CPU Certain bits reflect internal processor status and should be restored to their original values The CTL is a 16 bit latch t...

Page 180: ...r a debug session is completed i e when a OnCE command is issued with the GO and EX bits set and not ignored 16 11 4 Write Back Bus Register WBBR The write back bus register WBBR is used as a means of passing operand informa tion between the CPU and the external command controller Whenever the external command controller needs to read the contents of a register or memory location it forces the dev...

Page 181: ...any read access to the FIFO address causes the counter to increment and point to the next FIFO register The registers are serially available to the external command controller through the common FIFO address Figure 16 11 shows the block diagram of the PC FIFO Figure 16 11 OnCE PC FIFO PC FIFO Register 0 TDO TCK PC FIFO Register 1 PC FIFO Register 2 PC FIFO Register 3 PC FIFO Register 4 Instruction...

Page 182: ...s of communication between the OnCE external command controller and the MMC2001 Before starting any debug ging activity the external command controller must wait for an acknowledgment that the device has entered debug mode The external command controller communicates with the device by sending 8 bit commands to the OnCE command register and 16 to 128 bits of data to one of the other OnCE registers...

Page 183: ...TAG OnCE port The connector has two rows of seven pins with 0 1 inch center to center spacing between pins in each row and each column Figure 16 12 Recommended Connector Interface to JTAG OnCE Port TDI TDO TCLK GPIO SI TARGET_RESET KEY No Connect GND 1 2 3 4 5 6 7 8 9 10 10 kΩ 10 kΩ TOP VIEW 11 12 13 14 TARGET VDD GPIO SO DBEV 0 1 inch center to center 10 kΩ 10 kΩ TARGET VDD TARGET VDD TRST 10 kΩ ...

Page 184: ...CCE VCCI 3 6 V Battery Supply Voltage VCCB VCCE 1 0 VCCE V Input High Voltage VIH 0 7 VCCE VCCE 0 2 V Input Low Voltage VIL 0 3 0 2 VCCE V Input Leakage Current All Input Only Pins IIN 10 10 µA Hi Z Off State Leakage Current All Input Non Crystal Outputs and I O Pins IOZ 10 10 µA Signal Low Input Current TMS TDI TCK TRST DE ROW 7 0 IL 0 015 0 2 mA Signal High Input Current TMS TDI TCK TRST DE ROW ...

Page 185: ...CLK 8 34 MHz 1 CLKIN Period THRC 29 4 ns 2 CLKIN Rise Time for square wave input 3 ns 3 CLKIN Fall Time for square wave input 3 ns CLKIN Duty Cycle 45 55 CLKIN Input Voltage 0 8 VCCE Vpp Crystal Frequency 32 768 kHz Crystal Period TLRC 30 5 µs Table A 4 Reset MOD Timing Specifications Num Characteristic Expression Min Max Unit 11 RSTIN Duration to be Qualified as Valid 4 TLRC 0 05 122 12 µs 12 Del...

Page 186: ...le A 5 External Interrupt Timing Specifications Num Characteristic Symbol Min Max Unit 21 Minimum Edge Triggered INTn Width High 2 THRC 2 60 8 ns 22 Minimum Edge Triggered INTn Width Low 2 THRC 2 60 8 ns RSTIN All Pins RSTOUT 11 12 14 Reset Value 13 RSTOUT MOD 15 16 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 187: ...0 16 ns 36 CLKOUT Rise to OE EB Asserted Read OEA 1 2 0 16 ns 37 CLKOUT Rise to OE EB Negated Output Hold Read 2 0 ns 37 CLKOUT Rise to EB Negated Output Hold Write WEN 0 0 ns 38 CLKOUT Fall to EB Negated Output Hold Write WEN 1 0 ns 39 CLKOUT Fall to OE EB Asserted WSC 0 2 0 13 ns 40 CLKOUT Rise to OE EB Negated Output Hold WSC 0 2 0 ns 41 Data In Valid to CLKOUT rise setup 17 ns 42 CLKOUT Rise t...

Page 188: ...34 33 Address 41 Data In Read Data Out WSC 0 Write 43 45 CS OE EB WSC 0 42 44 40 39 32 31 OE EB 37 35 OEA 0 OE EB OEA 1 37 36 EB WEN 1 38 35 46 Data Out Write 47 WSC 0 R W 48 EB 37 35 WEN 0 Read Read Write Write Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 189: ... tw SCKL 4 512 CLK 56 Data Setup Time Inputs tsu 8 ns 57 Data Hold Time Inputs th 8 ns 58 Access Time Slave ta 1 SCLK 59 Disable Time Hold Time tdis 1 SCLK 60 Data Valid After Enable Edge tv s 5 ns 61 Data Hold Time Output After Enable Edge tho 0 ns 62 Rise Time 20 VDD to 70 VDD CL 20pF Manual Interval Mode Slave Mode trs 10 10 ns 63 Fall Time 20 VDD to 70 VDD CL 20pF Manual Interval Mode Slave Mo...

Page 190: ...ransmitted likely not to be LSB in slave mode 55 54 51 54 55 62 63 63 62 53 56 60 61 MSB OUT MSB IN 64 52 61 PD 59 58 60 SPI_EN Input SCLK Input POL 0 SCLK Input POL 1 SPI_MISO Output SPI_MOSI Input MSB OUT DATA LSB OUT MSB IN DATA LSB IN NOTE PD Port data is not defined but normally LSB of character previously transmitted likely not to be LSB in slave mode 54 55 51 55 54 63 62 62 63 53 56 60 61 5...

Page 191: ...N 64 52 61 TBD TBD NOTE The sequential transfer delay is determined by the settings in the SPI interval control register NOTE 62 SNS 1 SPI_EN Output SPI_EN Output SNS 0 SCLK Output POL 0 SCLK Output POL 1 SPI_MOSI Output SPI_MISO Input MSB OUT DATA LSB OUT TBD MSB IN DATA LSB IN 54 55 59 55 54 63 62 62 63 53 PD 56 60 TBD 61 52 57 MSB OUT MSB IN 64 NOTE The sequential transfer delay is determined b...

Page 192: ...y of Operation 0 CLK 2 MHz 92 TCK Clock Pulse Width Measured at 1 5 V 20 ns 93 TCK Rise and Fall Times 0 8 ns 94 TMS TDI Data Setup Time 7 ns 95 TMS TDI Data Hold Time 25 ns 96 TCK Low to TDO Data Valid 0 44 ns 97 TCK Low to TDO High Z 0 44 ns 98 TRST Assert Time 100 ns 99 TRST Setup Time to TCK Low 40 ns TCK VIH VIL 92 92 93 93 TCK TRST 98 99 Freescale Semiconductor I Freescale Semiconductor Inc ...

Page 193: ...E L I M I N A R Y Figure A 12 Test Access Port Timing TCK TDI TDO TDO TDO VIH VIL Input Data Valid Output Data Valid Output Data Valid TMS 96 94 95 97 96 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 194: ...67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 MMC2001 TOP VIEW OE R W DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DGND0 DVDD0 DATA3 DATA2 DATA1 DATA0 QGND QVCCH QVCC XVDD MOD XGND XOSC EXOSC XGND NOT USED VSTBY FVDD VBATT LVRSTIN RSTIN RSTOUT FGND CLKIN CLKOUT GPSOUT IF DATA11 DVDD1 GGND1 COL0 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 SPI_MISO HVDD HGND ...

Page 195: ...MOTOROLA PACKAGING AND PIN ASSIGNMENTS MMC2001 B 2 REFERENCE MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 196: ...2FFF Not Used Access causes transfer error 10003000 10003FFF Keypad Port Supervisor Only 10004000 10004FFF External Interface Module Supervisor Only 10005000 10005FFF Pulse width Modulator Supervisor Only 10006000 10006FFF Not Used Access causes transfer error 10007000 10007FFF GPIO Edge Port Supervisor Only 10008000 10008FFF Interval SPI Supervisor Only 10009000 10009FFF UART 0 Supervisor Only 10...

Page 197: ...gister NIER Access the 32 bit normal interrupt enable register with 32 bit loads and stores only Table C 2 Interrupt Controller Address Map Address Use Access 10000000 Interrupt Source Register INTSRC Supervisor Only 10000004 Normal Interrupt Enable Register NIER Supervisor Only 10000008 Fast Interrupt Enable Register FIER Supervisor Only 1000000C Normal Interrupt Pending Register NIPND Supervisor...

Page 198: ...ag x This bit enables the corresponding interrupt source to request a fast interrupt 0 Disable 1 Enable A reset operation clears this bit NIER Normal Interrupt Enable Register 10000004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN31 EN30 EN29 EN28 EN27 EN26 EN25 EN24 EN23 EN22 EN21 EN20 EN19 EN18 EN17 EN16 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN15 EN14 E...

Page 199: ...rrupt input lines which are asserted and are currently enabled to generate a normal interrupt C 2 5 Fast Interrupt Pending Register FIPND Access the 32 bit read only fast interrupt pending register with 32 bit loads only Figure C 5 Fast Interrupt Pending Register NIPND Normal Interrupt Pending Register 1000000C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NP31 NP30 NP29 NP28 NP27 NP26 NP25 NP24...

Page 200: ...egister with 32 bit loads and stores only Table C 3 Timer Reset Module Address Map Address Use Access 10001000 Reset Source Chip Configuration Register RSCR Supervisor Only 10001004 Time of Day Control Status Register TODCSR Supervisor Only 10001008 Time of Day Seconds Register TODSR Supervisor Only 1000100C Time of Day Fraction Register TODFR Supervisor Only 10001010 Time of Day Seconds Alarm Reg...

Page 201: ... bit is set however this bit is undefined This bit is cleared by writing to RSCR RST RSTIN Pin This bit is set when the RSTIN pin is asserted and qualified by the four cycle qualifier to reset the MMC2001 It is not affected by the other reset sources When the POR bit is set however this bit is undefined It is cleared by writing to RSCR POR Power On Reset This bit is set when an internal POR occurs...

Page 202: ... a 32 bit read write register that holds the number of elapsed seconds It is clocked by a 1 Hz signal generated as a carry from the TOD fraction register When TODSR is read the content of the fraction counter is latched into a holding buffer to be read later This prevents a fraction rollover between reads of the two registers from causing incorrect data to be read When TODSR is written the TODFR i...

Page 203: ...TOD Seconds Alarm Register TODSAR The time of day seconds alarm register is a 32 bit read write register which holds data in seconds to be compared to the TOD seconds register The comparison is made every 1 256 of a second if the alarm function is enabled by the AE bit in the TODCSR Writes to this register inhibit alarm compares until the TODFAR is written For proper alarm operation the fraction a...

Page 204: ...er WCR This register contains fields that control the operation of the watchdog in different modes of operation The write once bits can only be written once after a reset condi tion Subsequent attempts to write to them will not affect the data previously written Access this register with 32 bit loads and stores only TODSAR Time of Day Seconds Alarm Register 10001010 31 0 R TOD SECONDS ALARM REGIST...

Page 205: ...chdog not affected while in doze mode 1 Watchdog disabled while in doze mode C 3 8 Watchdog Service Register WSR When enabled the watchdog requires that a service sequence be written to the watchdog service register WSR This register controls the clearing of the watchdog counter to keep it from timing out and causing a reset If this register is not written with 0x5555 followed by 0xAAAA before the...

Page 206: ...rol This bit controls the function of the PIT in debug mode 0 PIT function is not affected while in debug mode 1 PIT function is frozen while in debug mode WSR Watchdog Service Register 10001020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W WATCHDOG SERVICE REGISTER RESET 0 0 0 0 0...

Page 207: ...ue contained in the modulus latch is reloaded into the counter when the counter reaches a count of zero or whether the counter rolls over from 0 to 0xFFFF 0 Counter rolls over to 0xFFFF 1 Counter is reloaded from the modulus latch EN PIT Enable This bit controls the PIT enable function 0 PIT is disabled 1 PIT is enabled C 3 10 PIT Data Register ITDR On a write the data becomes the new timer modulu...

Page 208: ... 7 6 5 4 3 2 1 0 R PIT DATA W RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ITADR PIT Alternate Data Register 1000102C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PIT COUNTER W RESET Table C 4 Keypad Port Address Map Address Use Access 10003000 Keypad Control Register KPCR Supervisor Only 10003002 Keypad Status Register ...

Page 209: ... keypress detect circuit The KPSR register is byte or halfword addressable Figure C 18 Keypad Status Register KRIE Key Release Interrupt Enable 0 No interrupt request is generated when KPKR is set 1 An interrupt request is generated when KPKR is set KDIE Key Depress Interrupt Enable 0 No interrupt request is generated when KPKD is set 1 An interrupt request is generated when KPKD is set KRSS Key R...

Page 210: ... is configured as input 1 COLx pin is configured as output KRDDx Keypad Row x Data Direction 0 ROWx pin is configured as input 1 ROWx pin is configured as output C 4 4 Keypad Data Register KPDR The 16 bit keypad data register is used to access the column and row data Data writ ten to this register is stored in an internal latch and for each pin configured as an out put the stored data is driven on...

Page 211: ... programmable output function For CS1 CS3 control registers bits two to 15 i e bits other than the PA and CSEN bits are undefined at reset Access these registers with 32 bit loads and stores only KPDR Keypad Data Register 10003006 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R KCD7 KCD6 KCD5 KCD4 KCD3 KCD2 KCD1 KCD0 KRD7 KRD6 KRD5 KRD4 KRD3 KRD2 KRD1 KRD0 W RESET Table C 5 EIM Address Map Address Use Acc...

Page 212: ...al SRAM two clock read and write access CSA 0 WSC 0001 and WWS 1 for access to Flash memory two clock read access and three clock write access EDC CSA and WSC to the appropriate number for access to an LCD controller CS0CR CS0 Control Register 10004000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R WSC WWS EDC CSA O...

Page 213: ...ycle is a read cycle to the same CS bank CSA Chip Select Assert This bit is used for devices that require additional address setup time and additional address data hold times It determines when the chip select is asserted and whether an idle cycle is inserted between back to back external transfers If WSC 0000 this bit is ignored 0 Chip select is asserted normally i e as early as possible No idle ...

Page 214: ...BC Enable Byte Control This bit is used to indicate which access types should assert the enable byte outputs EB 0 1 0 Read and write accesses are both allowed to assert the EB 0 1 outputs thus configuring them as byte enables 1 Only write accesses are allowed to assert the EB 0 1 outputs thus configuring them as byte write enables The EB 0 1 outputs should be configured as byte write enables for a...

Page 215: ...will result in TEA assertion to the CPU and no assertion of the chip select output When disabled the pin is a general purpose output controlled by the value of the PA control bit When CSEN0 is clear CS0 is inactive 1 Chip select is enabled and is asserted when an access address falls within the range specified in Table C 8 With the exception of CS0 this bit is cleared by reset disabling the chip s...

Page 216: ...sses are allowed to the internal RAM 1 User mode accesses are prohibited An attempted access to the internal RAM in user mode will result in TEA assertion to the CPU SPROM Internal ROM Supervisor Protect This bit is used to restrict accesses to the internal ROM space if the access is attempted in the user mode of CPU operation On reset this bit is set 0 User mode accesses are allowed to the intern...

Page 217: ...e cycles caused by EDC or CSA being set is delayed by one clock This ensures that all internal transfers can be externally monitored at the expense of performance 11 Reserved Table C 10 PWM Address Map Address Use Access 10005000 PWM0 Control Register PWMCR0 Supervisor Only 10005002 PWM0 Period Register PWMPR0 Supervisor Only 10005004 PWM0 Width Register PWMWR0 Supervisor Only 10005006 PWM0 Counte...

Page 218: ...is cleared to zero 10005024 PWM4 Width Register PWMWR4 Supervisor Only 10005026 PWM4 Counter Register PWMCTR4 Supervisor Only 10005028 PWM5 Control Register PWMCR5 Supervisor Only 1000502A PWM5 Period Register PWMPR5 Supervisor Only 1000502C PWM5 Width Register PWMWR5 Supervisor Only 1000502E PWM5 Counter Register PWMCTR5 Supervisor Only 10005030 to 10005FFF Reserved Supervisor Only 10006000 to 10...

Page 219: ...ounter in this manner must be done with caution to avoid unexpected pin behavior DATA PWM Data This bit indicates or controls the current state of the PWM pin When the pin is config ured as a general purpose output the logical value written to this bit is used to drive the pin When the pin is configured as a general purpose input the pin value is reflected by this bit When the pin is configured in...

Page 220: ...h an interrupt request may still be generated even though the counter is being disabled To avoid this write the interrupt enable control bit IRQ_EN to zero when disabling the counter 1 PWM is enabled and begins a new period The following events occur The output pin changes state to start a new period if width 0 and period 0 and width period The counter is released and begins counting The comparato...

Page 221: ...et resulting in a 100 duty cycle Figure C 26 PWM Width Registers WIDTH Pulse Width When the counter reaches the value in this register the output is reset PWMPR0 PWM0 Period Register 10005002 PWMPR1 PWM1 Period Register 1000500A PWMPR2 PWM2 Period Register 10005012 PWMPR3 PWM3 Period Register 1000501A PWMPR4 PWM4 Period Register 10005022 PWMPR5 PWM5 Period Register 1000502A 15 14 13 12 11 10 9 8 7...

Page 222: ...masked within the interrupt controller module The functionality of this register is independent of the programmed pin direction PWMCR0 PWM0 Counter Register 10005006 PWMCR1 PWM1 Counter Register 1000500E PWMCR2 PWM2 Counter Register 10005016 PWMCR3 PWM3 Counter Register 1000501E PWMCR4 PWM4 Counter Register 10005026 PWMCR5 PWM5 Counter Register 1000502E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 ...

Page 223: ... read write edge port data direction register EPDDR controls the direction of the port pins Setting any bit in this register configures the corresponding pin as an output Clearing any bit in this register configures the corresponding pin as an input Pin direction is independent of the level edge mode programmed Figure C 29 Edge Port Data Direction Register EPPAR Edge Port Pin Assignment Register 1...

Page 224: ...ted edge has been detected on the port pins Figure C 31 Edge Port Flag Register EPFx Edge Port Flag Bit x 0 Selected edge for INTx pin has not been detected 1 Selected edge for INTx pin has been detected Bits in this register are set when the programmed edge is detected on the corre sponding pin A bit remains set until cleared by writing it to a one Pin transitions do not affect this register if t...

Page 225: ...bit transfer then bits 15 to 9 are forced to zeros The value in this register is updated at the end of every transfer Tx DATA Transmit Data This write only register contains the data bits to be transmitted to the external device Data is copied from this register to the shift register at the time that the XCH bit is set As data is shifted MSB first outgoing data is MSB justified relative to the CLO...

Page 226: ...EN pin is asserted only when XCH is active The SPI_EN bit must be programmed to a one for any master mode transfer to occur In slave mode the ISPI state machine uses the input value on the SPI_EN pin and this register bit is ignored Further the SPI_EN register bit will not reflect the value of the SPI_EN pin in slave mode 0 Negated 1 Asserted SNS SPI_EN Sense The SNS bit controls the sense of the ...

Page 227: ... This bit enables disables the ISPI interrupt request output signal This bit is cleared to zero on reset 0 Interrupts disabled 1 Interrupts enabled PHA Phase This bit controls the phase shift of the SPI_CLK 0 Normal phase 1 Shift advance to opposite phase POL Polarity This bit controls the polarity of the SPI_CLK 0 Normal polarity 1 Inverted polarity SPIGP SPI_GP Control This bit controls the data...

Page 228: ...for the number of bits transferred 0 Loopback disabled 1 Loopback enabled IVL_EN Interval Mode Enable This bit when set places the ISPI in interval mode If the MSTR bit in the ISPI control register is cleared then the ISPI is operating in slave mode and this bit is ignored 0 ISPI is not operating in interval mode 1 ISPI is operating in interval mode if MSTR 1 INTERVAL COUNT In interval mode this r...

Page 229: ...SPI data register and when set indicates that an interrupt has been requested 0 No interrupt has been requested 1 An interrupt has been requested XCH Exchange This bit reads the value of XCH which indicates when the state machine is perform ing a transfer In manual mode XCH is set by writing the ISPI data register In interval mode XCH is set automatically by the interval timer In slave mode XCH is...

Page 230: ... Supervisor Only 10009090 to 10009FFF Reserved Supervisor Only UART1 1000A000 UART1 Receive Register U1RX Supervisor Only 1000A002 Not Used Supervisor Only 1000A004 to 1000A03E U1RX Echoes On Word Boundaries Supervisor Only 1000A040 UART1 Transmit Register U1TX Supervisor Only 1000A042 Reserved Supervisor Only 1000A044 to 1000A07E U1TX Echoes On Word Boundaries Supervisor Only 1000A080 UART1 Contr...

Page 231: ...RUN FRMERR BRK or PRERR This bit is updated and valid for each received character 0 No error status detected 1 Error status detected At reset this bit is cleared to zero OVRRUN Receiver Overrun When set this read only bit indicates that the receiver ignored data to prevent over writing the data in the FIFO Under normal circumstances this bit should never be set It indicates that the user s softwar...

Page 232: ...the current character was detected with a parity error The data is possibly corrupted This bit is updated for each character read from the FIFO While parity is disabled this bit always reads zero 0 No parity error detected for data in RX DATA field 1 Parity error detected for data in RX DATA field At reset this bit is cleared to zero RX DATA Received Data These read only bits are the received char...

Page 233: ...hen the transmitter has one or more slots avail able in the TX FIFO The fill level in the TX FIFO at which an interrupt is generated is controlled by the TxFL bits While this bit is negated the transmitter interrupt is dis abled 0 TX interrupt disabled 1 TX interrupt enabled At reset this bit is cleared to zero TXEN Transmitter Enable This bit enables or disables the transmitter While UARTEN and T...

Page 234: ...r If the RXD line is already low when the receiver is enabled the receiver does not recognize break characters since it requires a valid one to zero transition before it can accept any character 0 Receiver disabled 1 Receiver enabled At reset this bit is cleared to zero IREN Infrared Interface Enable This active high bit enables the infrared interface 0 Infrared interface disabled 1 Infrared inter...

Page 235: ...mode the DOZE bit affects operation of the UART If this bit is set when the system is in the doze mode the UART is disabled 0 UART unaffected while the MCU is in doze mode 1 UART disabled while the MCU is in doze mode At reset this bit is cleared to zero UART EN UART Enable This bit enables or disables the UART If this bit is cleared in the middle of a transmis sion the transmitter stops and drive...

Page 236: ...s bit is cleared to zero CTS CTS bit This bit controls the CTS pin while the CTSC bit is negated While CTSC is asserted this bit has no function 0 CTS pin is driven high inactive 1 CTS pin is driven low active At reset this bit is cleared to zero PREN Parity Enable This bit enables or disables the parity generator in the transmitter and parity checker in the receiver 0 Parity disabled 1 Parity ena...

Page 237: ... genera tor Figure C 40 UART BRG Register CD Clock Divider These bits determine the bit clock generator output rate The CD field is used to pre set a 12 bit counter that is decremented at the system clock rate The value 0x000 produces the maximum clock rate equal to the system clock The value 0xFFF pro duces the minimum clock rate divide by 4096 C 9 6 UART Status Register USR The read write UART s...

Page 238: ...et this bit indicates that the receive FIFO data level is above the threshold level specified by the RxFL field and a maskable interrupt is generated Refer to the RxFL bit description for setting the threshold level In conjunction with the CHARRDY bit host software can continue to read the RX FIFO in an interrupt service routine until the RX FIFO is empty This bit is automatically cleared when the...

Page 239: ...ot use this loopback if IR_EN is active 0 Normal receiver operation 1 Internal connect transmitter output to receiver input At reset this bit is cleared to zero LOOP IR Loop TX and RX for IR Test This bit controls a loopback from transmitter to receiver in the infrared interface 0 No IR loop 1 Connect IR transmit to IR receiver At reset this bit is cleared to zero C 9 8 UART Port Control Register ...

Page 240: ... UPCR If a port pin x is configured as a GPIO input then the corresponding PDx bit will reflect the value present on this pin If a port pin x is configured as a GPIO output then the value written into the corre sponding PDx bit will be reflected on the pin Note that since the CTS and RTS pins are not present for UART1 the corresponding port control register bits should be configured in a manner wh...

Page 241: ...mal operation if the EX bit is set The GO command is executed only if the operation is a read write to either CPUSCR or No register selected Otherwise the GO bit is ignored The processor leaves debug mode after the TAP controller update DR state is entered 0 Inactive no action taken 1 Execute instruction in IR EX Exit Command If the EX bit is set the processor leaves debug mode and resumes normal ...

Page 242: ...point Address Base Register B BABB 01001 Breakpoint Address Mask Register A BAMA 01010 Breakpoint Address Mask Register B BAMB 01011 CPU Scan Register CPUSCR 01100 No Register Selected Bypass 01101 OnCE Control Register OCR 01110 OnCE Status Register OSR 01111 Reserved Factory Test Control Register do not access 10000 Reserved MEM_BIST do not access 10001 10110 Reserved Bypass do not access 10111 ...

Page 243: ...tes when memory breakpoint B occurs while allowing the CPU to continue execution The PC FIFO remains frozen until the FRZO bit in the OSR is cleared Table C 21 Sequential Control Field Definition SQC 1 0 Meaning 00 Disable sequential control operation Memory breakpoints and trace operation are unaf fected by this field 01 Suspend normal trace counter operation until a breakpoint condition occurs f...

Page 244: ... BC0 Description 0 0 0 0 0 Breakpoint disabled 0 0 0 0 1 Qualify match with any access 0 0 0 1 0 Qualify match with any instruction access 0 0 0 1 1 Qualify match with any data access 0 0 1 0 0 Qualify match with any change of flow instruction access 0 0 1 0 1 Qualify match with any data write 0 0 1 1 0 Qualify match with any data read 0 0 1 1 1 Reserved 0 1 x x x Reserved 1 0 0 0 0 Reserved 1 0 0...

Page 245: ...set due to the CPU entering debug mode for another reason This bit is cleared on test logic reset or when debug mode is exited with the GO and EX bits set SWO Software Debug Occurrence This read only status bit is set when the processor enters debug mode of operation as a result of the execution of the bkpt instruction This bit is cleared on test logic reset or when debug mode is exited with the G...

Page 246: ...2 bit breakpoint address mask registers BAMA BAMB store memory break point base address masks BAMA and BAMB can be read or written through the OnCE serial interface Before enabling breakpoints the external command controller should load these registers C 10 7 Breakpoint Address Comparators Each breakpoint address comparator compares the current memory address stored in MAL with the contents of the...

Page 247: ...nd value of the first instruction to be executed following an update of the CPUSCR This gives the debug firmware the capability of updating processor registers by initializing the WBBR with the desired value setting the FFY bit and executing a mov instruc tion to the desired register FDB Force PSR Debug Mode A logical OR of this control bit with the PSR DB bit determines whether the proces sor is ...

Page 248: ...ue as a write back data value The FFY bit in the control state register forces the value of the WBBR to be substituted for the normal source value of a mov instruction thus allowing updates to processor registers to be performed C 10 13 Processor Status Register PSR The OnCE processor status register PSR is a 32 bit latch used to read or write the M CORE processor status register Whenever the exte...

Page 249: ...MOTOROLA PROGRAMMING REFERENCE MMC2001 C 54 REFERENCE MANUAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 250: ...e bit 7 11 C 20 CKOE bit 8 7 9 4 C 6 CKOS bit 9 3 C 6 Clear to send 4 7 11 2 CLK SEL field 15 6 C 25 CLKIN signal 4 5 CLKOUT Enable bit 8 7 9 4 C 6 CLKOUT signal 4 5 8 7 CLKOUT Source bit 9 3 C 6 CLKSRC bit 11 13 Clock Divider bit 11 13 C 42 input 4 5 input specifications A 2 module 8 1 block diagram 8 3 output 4 5 8 7 Select field 15 6 C 25 source 8 1 Source bit 11 13 CLOCK COUNT field 12 7 C 33 ...

Page 251: ...IMCR 7 11 C 20 Electrical characteristics A 1 EN bit 9 15 C 12 EN flags 10 3 C 3 Enable Byte Control bit 7 10 C 19 bytes 4 4 7 2 Fast Interrupt Flags 10 4 C 3 Normal Interrupt Flags 10 3 C 3 EPDDR 13 3 C 28 EPDR 13 3 C 29 EPFR 13 4 C 29 EPPAR 13 2 C 27 EPSR 2 3 ERR bit 11 7 C 36 Error Detect bit 11 7 C 36 EX bit 16 7 C 46 Exceptions cycles 2 14 processing 2 3 shadow registers 2 4 Exchange flag 12 ...

Page 252: ...it 12 6 C 32 IRTS bit 11 2 11 12 C 41 ISPI 12 1 block diagram 12 1 clock 12 4 Control Register 12 5 C 31 Data Register 12 5 C 30 Debug mode and 12 11 Enable bit 12 6 C 31 enable signal 12 4 general purpose output 12 4 Interval Control Register 12 8 C 33 interval mode 12 3 12 10 low power modes and 8 5 low power operation 12 11 manual mode 12 2 12 9 operation 12 1 programming model 12 4 C 30 signal...

Page 253: ... Master Mode bit 12 6 C 32 Master out slave in 12 4 Maximum ratings A 1 MBCA 16 14 C 51 MBCB 16 14 C 51 MBO bit 16 11 C 50 Memory Address Latch 16 13 C 51 Breakpoint 16 12 B A Control bits 16 10 C 49 B A Range Control bits 16 10 C 49 Counters 16 14 C 51 Occurrence bit 16 11 C 50 load and store 2 2 map MMC2001 3 1 peripheral modules 3 2 C 1 organization 2 5 MFCR instruction 2 4 MMC2001 memory map 3...

Page 254: ...52 Prefetch Transfer Code field 16 19 C 53 PREN bit 11 12 C 41 PRERR bit 11 8 C 37 Prescaler PWM 15 2 Privilege modes 2 3 supervisor 2 3 user 2 3 Processor Mode field 16 12 C 51 Processor Status Register 16 19 C 53 PROE bit 11 13 C 41 Program counter 2 2 2 3 Program Counter Register 16 18 C 51 Programming model edge port 13 2 EIM 7 7 interrupt controller 10 2 ISPI 12 4 C 30 KPP 14 2 C 13 M CORE 2 ...

Page 255: ...16 21 Shadow registers 2 3 2 4 SHEN bits 7 7 7 12 C 22 Show Cycle Enable bits 7 7 7 12 C 22 Signals 4 1 edge port 13 1 EIM 7 1 ISPI 12 3 KPP 14 2 M CORE bus 2 9 OnCE 16 3 UART 11 2 Slave mode 12 3 12 10 SNDBRK bit 11 11 C 40 SNS bit 12 6 C 31 Software Debug Occurrence bit 16 11 C 50 SP bit 7 6 7 10 C 19 SPCR 12 5 C 31 SPDR 12 5 C 30 SPI data master in slave out 4 8 data master out slave in 4 8 ena...

Page 256: ...C 43 U UART 11 1 block diagram 11 2 BRG Register 11 13 C 42 Control Register 1 11 9 C 38 Control Register 2 11 11 C 40 Data Direction Register 11 16 Debug mode and 11 24 Enable bit 11 11 C 40 general purpose I O 11 16 low power modes and 8 5 11 23 Port Control Register 11 16 C 44 Port Data Register 11 17 C 45 programming model 11 5 Receiver Register 11 7 C 36 signals 11 2 Status Register 11 14 C 4...

Page 257: ...te Wait State bit 7 9 C 18 Write Back Bus Register 16 17 16 19 C 53 WS bit 11 13 C 42 WSC bit 7 8 C 17 WSR 9 11 C 10 WSTP bit 9 11 C 10 WT field 9 10 C 10 WWS bit 7 9 C 18 X XCH bit 12 9 C 34 XOSCpin 4 5 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 258: ...inal 1 1 15 OCT 98 Section 1 1 Changed number of address lines in features list from 20 to 22 Section 11 2 1 Rewrote to clarify function of RTS pin Section 11 2 2 Rewrote to clarify function of CTS pin Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 259: ...n team Technical writing illustration and production editing performed with Adobe FrameMaker running on multiple platforms Cover graphic design by Bazzirk Inc of Austin Texas Printed by Imperial Lithographics Phoenix Arizona Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

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