viii
DSP56309UM/D MOTOROLA
Host Side Registers After Reset . . . . . . . . . . . . . . . . . . . 6-30
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
SERVICING THE HOST INTERFACE . . . . . . . . . . . . . . . . 6-31
HI08 Host Processor Data Transfer . . . . . . . . . . . . . . . . 6-31
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
HI08 PROGRAMMING MODEL QUICK REFERENCE. . . . 6-34
ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI)
7-1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
ENHANCEMENTS TO THE ESSI . . . . . . . . . . . . . . . . . . . . . 7-3
ESSI DATA AND CONTROL SIGNALS . . . . . . . . . . . . . . . . 7-4
Serial Transmit Data (STD) Signal . . . . . . . . . . . . . . . . . . 7-4
Serial Receive Data Signal (SRD) . . . . . . . . . . . . . . . . . . 7-4
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Serial Control Signal (SC0) . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Serial Control Signal (SC1) . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Serial Control Signal (SC2) . . . . . . . . . . . . . . . . . . . . . . . . 7-8
ESSI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 7-8
ESSI Control Register A (CRA). . . . . . . . . . . . . . . . . . . . 7-11
CRA Prescale Modulus Select PM[7:0] Bits 7Ð0 . . . . 7-11
CRA Reserved Bits 8Ð10 . . . . . . . . . . . . . . . . . . . . . . 7-11
CRA Prescaler Range (PSR) Bit 11 . . . . . . . . . . . . . . 7-11
CRA Frame Rate Divider Control DC[4:0] Bits 16Ð12 7-12
CRA Reserved Bit 17 . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
CRA Alignment Control (ALC) Bit 18 . . . . . . . . . . . . . 7-13
CRA Word-length Control (WL[2:0]) Bits 21Ð19 . . . . . 7-14
CRA Select SC1 (SSC1) Bit 22 . . . . . . . . . . . . . . . . . 7-14
CRA Reserved Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
ESSI Control Register B (CRB). . . . . . . . . . . . . . . . . . . . 7-15
CRB Serial Output Flags (OF0, OF1) Bits 0, 1. . . . . . 7-15
CRB Serial Output Flag 0 (OF0) Bit 0 . . . . . . . . . . 7-15
CRB Serial Output Flag 1 (OF1) Bit 1 . . . . . . . . . . 7-16
CRB Serial Control Direction 0 (SCD0) Bit 2 . . . . . . . 7-16
CRB Serial Control Direction 1 (SCD1) Bit 3 . . . . . . . 7-16
Summary of Contents for DSP56309
Page 25: ...xxii DSP56309UM D MOTOROLA Figure D 25 Port E Registers PCRE PRRE PDRE D 39 ...
Page 30: ...MOTOROLA DSP56309UM D 1 1 SECTION 1 DSP56309 OVERVIEW ...
Page 47: ...1 18 DSP56309UM D MOTOROLA DSP56309 Overview DSP56309 Architecture Overview ...
Page 48: ...MOTOROLA DSP56309UM D 2 1 SECTION 2 SIGNAL CONNECTION DESCRIPTIONS ...
Page 85: ...2 38 DSP56309UM D MOTOROLA Signal Connection Descriptions OnCE JTAG Interface ...
Page 86: ...MOTOROLA DSP56309UM D 3 1 SECTION 3 MEMORY CONFIGURATION ...
Page 104: ...MOTOROLA DSP56309UM D 4 1 SECTION 4 CORE CONFIGURATION ...
Page 124: ...MOTOROLA DSP56309UM D 5 1 SECTION 5 GENERAL PURPOSE I O ...
Page 125: ...5 2 DSP56309UM D MOTOROLA General Purpose I O 5 1 INTRODUCTION 5 3 5 2 PROGRAMMING MODEL 5 3 ...
Page 128: ...MOTOROLA DSP56309UM D 6 1 SECTION 6 HOST INTERFACE HI08 ...
Page 166: ...MOTOROLA DSP56309UM D 7 1 SECTION 7 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI ...
Page 212: ...MOTOROLA DSP56309UM D 8 1 SECTION 8 SERIAL COMMUNICATION INTERFACE SCI ...
Page 241: ...8 30 DSP56309UM D MOTOROLA Serial Communication Interface SCI GPIO Signals and Registers ...
Page 242: ...MOTOROLA DSP56309UM D 9 1 SECTION 9 TRIPLE TIMER MODULE ...
Page 269: ...9 28 DSP56309UM D MOTOROLA Triple Timer Module Timer Operational Modes ...
Page 270: ...MOTOROLA DSP56309UM D 10 1 SECTION 10 ON CHIP EMULATION MODULE ...
Page 302: ...MOTOROLA DSP56309UM D 11 1 SECTION 11 JTAG PORT ...
Page 369: ...C 22 DSP56309UM D MOTOROLA DSP56309 BSDL Listing ...
Page 370: ...MOTOROLA DSP56309UM D D 1 APPENDIX D PROGRAMMING REFERENCE ...
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