Motorola DSP56309 User Manual Download Page 412

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MOTOROLA

DSP56309UM/D I-3

bus interface unit

B-13

direct memory access

B-10

DMA

B-10

enhanced serial communication interface

ESSI

exception processing

HI08

host interface

i/o port programming

interrupt

phase locked loop

PLL

SCI

serial communication interface

timer module

ESSI

after reset

asynchronous operating mode

frame sync length

frame sync polarity

frame sync selection

frame sync word length

GPIO functionality

initialization

interrupts

Network mode

Normal mode

operating mode

operating modes

Port Control Register (PCR)

7-43

Port Data Register (PDR)

7-45

Port Direction Register (PRR)

7-44

programming model

7-8

synchronous operating mode

7-40

ESSI Control Register A (CRA)

7-11

ESSI Mode Select bit (MOD)

7-20

ESSI Receive Data Register (RX)

7-33

ESSI Receive Enable bit (RE)

7-26

ESSI Receive Exception Interrupt Enable bit

(REIE)

7-27

ESSI Receive Interrupt Enable bit (RIE)

7-26

ESSI Receive Last Slot Interrupt Enable bit

(RLIE)

7-27

ESSI Receive Shift Register

7-33

ESSI Receive Slot Mask Registers (RSMA,

RSMB)

7-35

ESSI Status Register (SSISR)

7-27

ESSI Time Slot Register (TSR)

7-34

ESSI Transmit 0 Enable bit (TE0)

7-24

ESSI Transmit 1 Enable bit (TE1)

7-23

ESSI Transmit 2 Enable bit (TE2)

7-22

ESSI Transmit Data registers (TX2, TX1, TX0)

7-34

ESSI Transmit Exception Interrupt Enable bit

(TEIE)

7-27

ESSI Transmit Interrupt Enable bit (TIE)

7-26

ESSI Transmit Last Slot Interrupt Enable bit

(TLIE)

7-26

ESSI Transmit Shift Registers

7-33

ESSI Transmit Slot Mask Registers (TSMA,

TSMB)

ESSI0

ESSI0 (GPIO)

ESSI1

ESSI1 (GPIO)

EX bit

exception processing equates

B-7

Exit Command bit (EX)

expanded mode

EXTAL

EXTAL signal

external address bus

external bus control

external clock/crystal input

2-7

external data bus

2-9

external interrupt request A signal

2-14

external interrupt request B signal

2-15

external interrupt request C signal

2-15

external interrupt request D signal

2-16

external memory expansion port

2-9

EXTEST instruction

11-8

FE bit

8-15

Frame Rate Divider Control bits (DC4ÐDC0)

7-12

Frame Sync Length bits (FSL1ÐFSL0)

7-17

Frame Sync Polarity bit (FSP)

7-17

Frame Sync Relative Timing bit (FSR)

7-17

frame sync selection

ESSI

7-41

Framing Error Flag bit (FE)

8-15

frequency

operation

FSL1ÐFSL0 bits

FSP bit

FSR bit

functional groups

general purpose input/output (GPIO)

2-34

Global Data Bus

1-13

Summary of Contents for DSP56309

Page 1: ...ee downloadable datasheets Over one million datasheets Optimized search function Rapid quote option Free unlimited downloads Visit www datasheetdirect com to get your free datasheets This datasheet has been downloaded by http www datasheetdirect com ...

Page 2: ...EMORY CONFIGURATION CORE CONFIGURATION GENERAL PURPOSE I O HOST INTERFACE HI08 ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE SCI TIMER MODULE ON CHIP EMULATION MODULE JTAG PORT C BSDL LISTING I INDEX D PROGRAMMING REFERENCE A BOOTSTRAP PROGRAM B EQUATES ...

Page 3: ...EMORY CONFIGURATION CORE CONFIGURATION GENERAL PURPOSE I O HOST INTERFACE HI08 ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE SCI TIMER MODULE ON CHIP EMULATION MODULE JTAG PORT C BSDL LISTING I INDEX D PROGRAMMING REFERENCE A BOOTSTRAP PROGRAM B EQUATES ...

Page 4: ...DSP56309 24 Bit Digital Signal Processor UserÕs Manual Motorola Incorporated Semiconductor Products Sector DSP Division 6501 William Cannon Drive West Austin TX 78735 8598 Rev 0 ...

Page 5: ...her notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not authorized for use as components in life support devices or systems intended for surgical impl...

Page 6: ...lator MAC 1 9 1 6 2 Address Generation Unit AGU 1 9 1 6 3 Program Control Unit PCU 1 10 1 6 4 PLL and Clock Oscillator 1 11 1 6 5 JTAG TAP and OnCE Module 1 11 1 6 6 On Chip Memory 1 12 1 6 7 Off Chip Memory Expansion 1 12 1 7 INTERNAL BUSES 1 13 1 8 DSP56309 BLOCK DIAGRAM 1 14 1 9 DIRECT MEMORY ACCESS DMA 1 15 1 10 DSP56309 ARCHITECTURE OVERVIEW 1 15 1 10 1 GPIO Functionality 1 15 1 10 2 Host Int...

Page 7: ...27 2 10 SERIAL COMMUNICATION INTERFACE SCI 2 32 2 11 TIMERS 2 33 2 12 ONCE JTAG INTERFACE 2 35 SECTION 3 MEMORY CONFIGURATION 3 1 3 1 MEMORY SPACES 3 3 3 1 1 Program Memory Space 3 3 3 1 2 Data Memory Spaces 3 3 3 1 2 1 X Data Memory Space 3 4 3 1 2 2 Y Data Memory Space 3 4 3 1 3 Memory Space Configuration 3 5 3 2 RAM CONFIGURATION 3 5 3 2 1 On Chip Program Memory Program RAM 3 6 3 2 2 On Chip X ...

Page 8: ...NTERRUPT SOURCES AND PRIORITIES 4 9 4 4 1 Interrupt Sources 4 9 4 4 2 Interrupt Priority Levels 4 12 4 4 3 Interrupt Source Priorities Within an IPL 4 14 4 5 DMA REQUEST SOURCES 4 16 4 6 OPERATING MODE REGISTER OMR 4 17 4 7 PLL CONTROL REGISTER 4 18 4 7 1 PCTL PLL Multiplication Factor Bits 0Ð11 4 18 4 7 2 PCTL XTAL Disable Bit XTLD Bit 16 4 18 4 7 3 PCTL Predivider Factor Bits PD0ÐPD3 Bits 20Ð23 ...

Page 9: ...HCR Reserved Bits 5 15 6 10 6 5 4 Host Status Register HSR 6 11 6 5 4 1 HSR Host Receive Data Full HRDF Bit 0 6 11 6 5 4 2 HSR Host Transmit Data Empty HTDE Bit 1 6 11 6 5 4 3 HSR Host Command Pending HCP Bit 2 6 11 6 5 4 4 HSR Host Flags 0 1 HF 1 0 Bits 3 4 6 11 6 5 4 5 HSR Reserved Bits 5 15 6 11 6 5 5 Host Base Address Register HBAR 6 12 6 5 5 1 HBAR Base Address BA 10 3 Bits 0 7 6 12 6 5 5 2 H...

Page 10: ...equest Enable RREQ Bit 0 6 23 6 6 1 2 ICR Transmit Request Enable TREQ Bit 1 6 23 6 6 1 3 ICR Double Host Request HDRQ Bit 2 6 23 6 6 1 4 ICR Host Flag 0 HF0 Bit 3 6 24 6 6 1 5 ICR Host Flag 1 HF1 Bit 4 6 24 6 6 1 6 ICR Host Little Endian HLEND Bit 5 6 24 6 6 1 7 ICR Reserved Bit 6 6 24 6 6 1 8 ICR Initialize Bit INIT Bit 7 6 24 6 6 2 Command Vector Register CVR 6 25 6 6 2 1 CVR Host Vector HV 6 0...

Page 11: ... 3 6 Serial Control Signal SC2 7 8 7 4 ESSI PROGRAMMING MODEL 7 8 7 4 1 ESSI Control Register A CRA 7 11 7 4 1 1 CRA Prescale Modulus Select PM 7 0 Bits 7Ð0 7 11 7 4 1 2 CRA Reserved Bits 8Ð10 7 11 7 4 1 3 CRA Prescaler Range PSR Bit 11 7 11 7 4 1 4 CRA Frame Rate Divider Control DC 4 0 Bits 16Ð12 7 12 7 4 1 5 CRA Reserved Bit 17 7 13 7 4 1 6 CRA Alignment Control ALC Bit 18 7 13 7 4 1 7 CRA Word ...

Page 12: ... RIE Bit 19 7 26 7 4 2 20 Transmit Last Slot Interrupt Enable TLIE Bit 20 7 26 7 4 2 21 Receive Last Slot Interrupt Enable RLIE Bit 21 7 27 7 4 2 22 Transmit Exception Interrupt Enable TEIE Bit 22 7 27 7 4 2 23 Receive Exception Interrupt Enable REIE Bit 23 7 27 7 4 3 ESSI Status Register SSISR 7 27 7 4 3 1 SSISR Serial Input Flag 0 IF0 Bit 0 7 28 7 4 3 2 SSISR Serial Input Flag 1 IF1 Bit 1 7 28 7...

Page 13: ... SIGNALS AND REGISTERS 7 43 7 6 1 Port Control Register PCR 7 43 7 6 2 Port Direction Register PRR 7 44 7 6 3 Port Data Register PDR 7 45 SECTION 8 SERIAL COMMUNICATION INTERFACE SCI 8 1 8 1 INTRODUCTION 8 3 8 2 SCI I O SIGNALS 8 3 8 2 1 Receive Data RXD 8 4 8 2 2 Transmit Data TXD 8 4 8 2 3 SCI Serial Clock SCLK 8 4 8 3 SCI PROGRAMMING MODEL 8 4 8 3 1 SCI Control Register SCR 8 8 8 3 1 1 SCR Word...

Page 14: ...E Bit 5 8 14 8 3 2 7 SSR Framing Error Flag FE Bit 6 8 15 8 3 2 8 SSR Received Bit 8 R8 Address Bit 7 8 15 8 3 3 SCI Clock Control Register SCCR 8 15 8 3 3 1 SCCR Clock Divider CD 11 0 Bits 11Ð0 8 16 8 3 3 2 SCCR Clock Out Divider COD Bit 12 8 16 8 3 3 3 SCCR SCI Clock Prescaler SCP Bit 13 8 17 8 3 3 4 SCCR Receive Clock Mode Source RCM Bit 14 8 17 8 3 3 5 SCCR Transmit Clock Source Bit TCM Bit 15...

Page 15: ...gister TCSR 9 9 9 3 4 1 Timer Enable TE Bit 0 9 9 9 3 4 2 Timer Overflow Interrupt Enable TOIE Bit 1 9 9 9 3 4 3 Timer Compare Interrupt Enable TCIE Bit 2 9 10 9 3 4 4 Timer Control TC 3 0 Bits 4 7 9 10 9 3 4 5 Inverter INV Bit 8 9 11 9 3 4 6 Timer Reload Mode TRM Bit 9 9 13 9 3 4 7 Direction DIR Bit 11 9 14 9 3 4 8 Data Input DI Bit 12 9 14 9 3 4 9 Data Output DO Bit 13 9 14 9 3 4 10 Prescaler Cl...

Page 16: ... SECTION 10 ON CHIP EMULATION MODULE 10 1 10 1 INTRODUCTION 10 3 10 2 ONCE MODULE SIGNALS 10 3 10 3 DEBUG EVENT DE 10 4 10 4 ONCE CONTROLLER 10 4 10 4 1 OnCE Command Register OCR 10 5 10 4 1 1 Register Select RS4ÐRS0 Bits 0Ð4 10 5 10 4 1 2 Exit Command EX Bit 5 10 5 10 4 1 3 GO Command GO Bit 6 10 6 10 4 1 4 Read Write Command R W Bit 7 10 6 10 4 2 OnCE Decoder ODEC 10 8 10 4 3 OnCE Status and Con...

Page 17: ... 5 6 8 Reserved Bits 12 15 10 15 10 6 ONCE TRACE LOGIC 10 15 10 7 METHODS OF ENTERING DEBUG MODE 10 16 10 7 1 External Debug Request During RESET Assertion 10 16 10 7 2 External Debug Request During Normal Activity 10 16 10 7 3 Executing the JTAG DEBUG_REQUEST Instruction 10 17 10 7 4 External Debug Request During Stop 10 17 10 7 5 External Debug Request During Wait 10 17 10 7 6 Software Request D...

Page 18: ...ORT ONCE MODULE INTERACTION 10 29 SECTION 11 JTAG PORT 11 1 11 1 INTRODUCTION 11 3 11 2 JTAG SIGNALS 11 4 11 2 1 Test Clock TCK 11 5 11 2 2 Test Mode Select TMS 11 5 11 2 3 Test Data Input TDI 11 5 11 2 4 Test Data Output TDO 11 5 11 2 5 Test Reset TRST 11 5 11 3 TAP CONTROLLER 11 6 11 3 1 Boundary Scan Register BSR 11 7 11 3 2 Instruction Register 11 7 11 3 2 1 EXTEST B 3 0 0000 11 8 11 3 2 2 SAM...

Page 19: ... MEMORY ACCESS DMA EQUATES B 10 B 8 PHASE LOCKED LOOP PLL EQUATES B 12 B 9 BUS INTERFACE UNIT BIU EQUATES B 13 B 10 INTERRUPT EQUATES B 15 APPENDIX C DSP56309 BSDL LISTING C 1 APPENDIX D PROGRAMMING REFERENCE D 1 D 1 INTRODUCTION D 3 D 1 1 Peripheral Addresses D 3 D 1 2 Interrupt Addresses D 3 D 1 3 Interrupt Priorities D 3 D 1 4 Programming Sheets D 3 D 2 INTERNAL I O MEMORY MAP D 4 D 3 INTERRUPT...

Page 20: ...tion Cache Enabled 1 0 1 3 15 Figure 3 7 16 bit Space with Switched Program RAM 1 1 0 3 16 Figure 3 8 16 bit Space Switched Program RAM Instruction Cache 3 17 Figure 4 1 Interrupt Priority Register C IPR C X FFFFFF 4 13 Figure 4 2 Interrupt Priority Register P IPR P X FFFFFE 4 13 Figure 4 3 DSP56309 Operating Mode Register OMR 4 17 Figure 4 4 PLL Control PCTL Register 4 18 Figure 4 5 Identificatio...

Page 21: ...6 22 Figure 6 13 Command Vector Register CVR 6 25 Figure 6 14 Interface Status Register 6 26 Figure 6 15 Interrupt Vector Register IVR 6 28 Figure 6 16 HI08 Host Request Structure 6 33 Figure 7 1 ESSI Block Diagram 7 5 Figure 7 2 ESSI Control Register A CRA 7 9 Figure 7 3 ESSI Control Register B CRB 7 9 Figure 7 4 ESSI Status Register SSISR 7 9 Figure 7 5 ESSI Transmit Slot Mask Register A TSMA 7 ...

Page 22: ...ing Model SHFD 1 7 32 Figure 7 18 Port Control Register PCR PCRC X FFFFBF 7 44 Figure 7 19 Port Direction Register PRR PRRC X FFFFBE 7 44 Figure 7 20 Port Data Register PDR PDRC X FFFFBD 7 45 Figure 8 1 SCI Control Register SCR 8 5 Figure 8 2 SCI Status Register SSR 8 5 Figure 8 3 SCI Clock Control Register SCCR 8 5 Figure 8 4 SCI Data Word Formats 8 6 Figure 8 5 16 x Serial Clock 8 16 Figure 8 6 ...

Page 23: ...re 10 4 OnCE Command Register 10 5 Figure 10 5 OnCE Status and Control Register OSCR 10 8 Figure 10 6 OnCE Memory Breakpoint Logic 0 10 10 Figure 10 7 OnCE Breakpoint Control Register OBCR 10 12 Figure 10 8 OnCE Trace Logic Block Diagram 10 15 Figure 10 9 OnCE Pipeline Information and GDB Registers 10 19 Figure 10 10 OnCE Trace Buffer 10 22 Figure 11 1 TAP Block Diagram 11 4 Figure 11 2 TAP Contro...

Page 24: ...nsmit Data Registers D 25 Figure D 12 ESSI Control Register A CRA D 26 Figure D 13 ESSI Control Register B CRB D 27 Figure D 14 ESSI Status Register SSISR D 28 Figure D 15 ESSR Transmit and Receive Slot Mask Registers TSM RSM D 29 Figure D 16 SCI Control Register SCR D 30 Figure D 17 SCI Status and Clock Control Registers SSR SCCR D 31 Figure D 18 SCI Receive and Transmit Data Registers SRX TRX D ...

Page 25: ...xxii DSP56309UM D MOTOROLA Figure D 25 Port E Registers PCRE PRRE PDRE D 39 ...

Page 26: ...ls 2 9 Table 2 7 External Data Bus Signals 2 10 Table 2 8 External Bus Control Signals 2 10 Table 2 9 Interrupt and Mode Control 2 14 Table 2 10 Host Port Usage Considerations 2 17 Table 2 11 Host Interface 2 18 Table 2 12 Enhanced Synchronous Serial Interface 0 ESSI0 2 24 Table 2 13 Enhanced Synchronous Serial Interface 1 ESSI1 2 28 Table 2 14 Serial Communication Interface SCI 2 32 Table 2 15 Tr...

Page 27: ...12 Table 4 4 Interrupt Source Priorities within an IPL 4 14 Table 4 5 DMA Request Sources 4 16 Table 6 1 HI08 Signal Definitions for Various Operational Modes 6 6 Table 6 2 HI08 Data Strobe Signals 6 6 Table 6 3 HI08 Host Request Signals 6 6 Table 6 4 Host Command Interrupt Priority List 6 10 Table 6 5 HDR and HDDR Functionality 6 18 Table 6 6 DSP Side Registers after Reset 6 19 Table 6 7 Host Sid...

Page 28: ...t 8 23 Table 8 4 Port Control Register and Port Direction Register Bits 8 28 Table 9 1 Prescaler Source Selection 9 8 Table 9 2 Timer Control Bits 9 10 Table 9 3 Inverter INV Bit Operation 9 12 Table 10 1 EX Bit Definition 10 6 Table 10 2 GO Bit Definition 10 6 Table 10 3 R W Bit Definition 10 6 Table 10 4 OnCE Register Select Encoding 10 6 Table 10 5 Core Status Bits Description 10 9 Table 10 6 M...

Page 29: ...Sequencing for DEBUG_REQUEST 10 29 Table 10 13 TMS Sequencing for ENABLE_ONCE 10 30 Table 10 14 TMS Sequencing for Reading Pipeline Registers 10 31 Table 11 1 JTAG Instructions 11 8 Table 11 2 DSP56309 BSR Bit Definitions 11 13 Table D 1 Internal I O Memory Map D 4 Table D 2 Interrupt Sources D 11 Table D 3 Interrupt Source Priorities within an IPL D 13 ...

Page 30: ...MOTOROLA DSP56309UM D 1 1 SECTION 1 DSP56309 OVERVIEW ...

Page 31: ...L ORGANIZATION 1 3 1 3 MANUAL CONVENTIONS 1 5 1 4 DSP56309 FEATURES 1 6 1 5 DSP56309 CORE DESCRIPTION 1 7 1 6 DSP56300 CORE FUNCTIONAL BLOCKS 1 8 1 7 INTERNAL BUSES 1 13 1 8 DSP56309 BLOCK DIAGRAM 1 14 1 9 DIRECT MEMORY ACCESS DMA 1 15 1 10 DSP56309 ARCHITECTURE OVERVIEW 1 15 ...

Page 32: ...nductor Sales Office or authorized distributor To receive the latest information about this DSP access the Motorola DSP home page at the address on the back cover of this document 1 2 MANUAL ORGANIZATION This manual contains the following sections and appendices Section 1ÑDSP56309 Overview Ð Features list and block diagram Ð Related documentation needed to use this chip Ð The organization of this ...

Page 33: ...lex serial port for serial communication to DSPs microcontrollers or other peripherals such as modems or other RS 232 devices Section 9ÑTriple Timer Module Ð The three identical internal timers event counter devices Section 10ÑOn Chip Emulation Module Ð The On Chip Emulation OnCEª module which is accessed through the JTAG port Section 11ÑJTAG Port Ð Specifics of the Joint Test Action Group JTAG po...

Page 34: ...low true active low signal is pulled low to ground The word ÒdeassertÓ means that a high true signal is pulled low to ground or that a low true signal is pulled high to VCC See Table 1 1 Pins or signals that are asserted low made active when pulled to ground Ð In text have an overbar For example RESET is asserted low Ð In code examples have a tilde in front of their names In Example 1 1 line 3 ref...

Page 35: ...orola s popular DSP56000 core family while retaining code compatibility The DSP56300 core family offers a new level of performance in speed and power provided by its rich instruction set and low power dissipation enabling a new generation of wireless telecommunications and multimedia products The DSP56300 core is composed of the data arithmetic logic unit Data ALU address generation unit AGU progr...

Page 36: ...es this manual describes pinout memory and peripheral features 1 5 1 General Features 80 100 million instructions per second MIPS with a 80 100 MHz clock at 3 0 3 6 V Object code compatible with the DSP56000 core Highly parallel instruction set 1 5 2 Hardware Debugging Support On Chip Emulation OnCEÔ module Joint Test Action Group JTAG test access port TAP Address trace mode reflects internal prog...

Page 37: ...field unit comprising a 56 bit parallel barrel shifter fast shift and normalization bit stream generation and parsing Conditional ALU instructions 24 bit or 16 bit arithmetic support under software control Four 24 bit input general purpose registers X1 X0 Y1 and Y0 Six Data ALU registers A2 A1 A0 B2 B1 and B0 that are concatenated into two general purpose 56 bit accumulators A and B accumulator sh...

Page 38: ...Generation Unit AGU The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers that generate the addresses It implements four types of arithmetic linear modulo multiple wrap around modulo and reverse carry The AGU operates in parallel with other chip resources to minimize address generation overhead The AGU i...

Page 39: ...truction latch and generates all signals necessary for pipeline control The PAG contains all the hardware needed for program address generation system stack and loop control The PIC arbitrates among all interrupt requests internal interrupts as well as the five external requests IRQA IRQB IRQC IRQD and NMI and generates the appropriate interrupt vector address PCU features include the following Po...

Page 40: ...rated by a system The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system 1 6 5 JTAG TAP and OnCE Module The DSP56300 core provides a dedicated user accessible Test Access Port TAP that is fully compatible with the IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture Problems associated with testing high dens...

Page 41: ...d off chip under software control More information about the internal memory is provided in Section 3ÑMemory Configuration Program RAM instruction cache X data RAM and Y data RAM size are programmable as indicated in Table 1 2 Table 1 2 On Chip Memory There is an on chip 192 x 24 bit bootstrap ROM 1 6 7 Off Chip Memory Expansion Memory can be expanded off chip to do the following Data memory expan...

Page 42: ...am RAM X memory expansion bus XM_EB to X memory Y memory expansion bus YM_EB to Y memory Global data bus GDB between PCU and other core structures Program data bus PDB for carrying program data throughout the core X memory data bus XDB for carrying X data throughout the core Y memory data bus YDB for carrying Y data throughout the core Program address bus PAB for carrying program memory addresses ...

Page 43: ...300 6 16 24 Bit 24 18 X Data RAM Y Data RAM DDB DAB Memory Expansion Area Peripheral Core YM_EB XM_EB PM_EB PIO_EB Expansion Area 6 SCI Interface JTAG 6 3 RESET MODD IRQA PINIT NMI 2 Boot strap ROM EXTAL XTAL ADDRESS CONTROL DATA Triple Timer Host Interface HI08 ESSI Interface Address Generation Unit Six Channel DMA Unit Program Interrupt Controller Program Decode Controller Program Address Genera...

Page 44: ...nnection to a number of industry standard microcomputers microprocessors and DSPs Two enhanced synchronous serial interfaces ESSI0 and ESSI1 each with one receiver and three transmitters allows six channel home theater Serial communications interface SCI with baud rate generator Triple timer module Up to 34 programmable general purpose input output GPIO pins depending on which peripherals are enab...

Page 45: ... 3 Enhanced Synchronous Serial Interface ESSI On the DSP56309 are two independent and identical ESSIs Each ESSI has a full duplex serial port for communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals that implement the Motorola SPI The ESSI consists of independent transmitter and receiver sections and a common ESSI ...

Page 46: ...rogrammable baud rate generator provides the transmit and receive clocks An enable vector and an interrupt vector have been included so that the baud rate generator can function as a general purpose timer when it is not being used by the SCI or when the interrupt timing is the same as that used by the SCI 1 10 5 Timer Module The triple timer module is composed of a common 21 bit prescaler and thre...

Page 47: ...1 18 DSP56309UM D MOTOROLA DSP56309 Overview DSP56309 Architecture Overview ...

Page 48: ...MOTOROLA DSP56309UM D 2 1 SECTION 2 SIGNAL CONNECTION DESCRIPTIONS ...

Page 49: ...ROUND 2 6 2 4 CLOCK 2 7 2 5 PHASE LOCKED LOOP PLL 2 8 2 6 EXTERNAL MEMORY EXPANSION PORT PORT A 2 9 2 7 INTERRUPT AND MODE CONTROL 2 14 2 8 HOST INTERFACE HI08 2 16 2 9 ENHANCED SYNCHRONOUS SERIAL INTERFACE 2 24 2 10 SERIAL COMMUNICATION INTERFACE SCI 2 32 2 11 TIMERS 2 33 2 12 ONCE JTAG INTERFACE 2 35 ...

Page 50: ...Address Bus Port A1 18 Table 2 6 Data Bus 24 Table 2 7 Bus Control 13 Table 2 8 Interrupt and Mode Control 5 Table 2 9 Host Interface HI08 Port B2 16 Table 2 11 Enhanced Synchronous Serial Interface ESSI Ports C and D3 12 Table 2 12 and Table 2 13 Serial Communication Interface SCI Port E4 3 Table 2 14 Timer 3 Table 2 15 OnCE JTAG Port 6 Table 2 16 Note 1 Port A signals define the external memory ...

Page 51: ...C5 Port D GPIO PD0ÐPD2 PD3 PD4 PD5 GPIO TIO0 TIO1 TIO2 Port A AA0601 Notes 1 The HI08 port supports a non multiplexed or a multiplexed bus single or double Data Strobe DS and single or double Host Request HR configurations Since each of these modes is configured independently any combination of these modes is possible These HI08 signals can also be configured alternately as GPIO signals PB0ÐPB15 S...

Page 52: ... inputs except VCCQL The user must provide adequate external decoupling capacitors There are three VCCQH inputs VCCA 3 Address Bus PowerÑVCCA is an isolated power for sections of the address bus I O drivers This input must be tied externally to all other chip power inputs except VCCQL The user must provide adequate external decoupling capacitors There are three VCCA inputs VCCD 4 Data Bus PowerÑVC...

Page 53: ...icated for PLL use The connection should be provided with an extremely low impedance path to ground VCCP should be bypassed to GNDP by a 0 47 mF capacitor located as close as possible to the chip package There is one GNDP connection GNDP1 PLL Ground 1ÑGNDP1 is a ground dedicated for PLL use The connection should be provided with an extremely low impedance path to ground There is one GNDP1 connecti...

Page 54: ...p ground connections The user must provide adequate external decoupling capacitors There is one GNDH connection GNDS 2 ESSI SCI and Timer GroundÑGNDS is an isolated ground for the ESSI SCI and timer I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There are two GNDS connections Note These designat...

Page 55: ...Input PLL CapacitorÑPCAP is an input connecting an off chip capacitor to the PLL filter Connect one capacitor terminal to PCAP and the other terminal to VCCP If the PLL is not used PCAP can be tied to VCC tied to GND or left floating CLKOUT Output Chip driven Clock OutputÑCLKOUT provides an output clock synchronized to the internal core clock phase If the PLL is enabled and both the multiplication...

Page 56: ...L control register determining whether the PLL is enabled or disabled After RESET deassertion and during normal instruction processing the PINIT NMI Schmitt trigger input is a negative edge triggered Non Maskable Interrupt NMI request internally synchronized to CLKOUT Table 2 6 External Address Bus Signals Signal Name Type State During Reset Signal Description A0ÐA17 Output Tri stated Address BusÑ...

Page 57: ...se D0ÐD23 are weakly driven by the bus keeper Table 2 8 External Bus Control Signals Signal Name Type State During Reset Signal Description AA0Ð AA3 RAS0Ð RAS3 Output Tri stated Address Attribute or Row Address StrobeÑWhen defined as AA these signals can be used as chip selects or additional address lines When defined as RAS these signals can be used as RAS for DRAM interface These signals are tri...

Page 58: ...e and is deasserted before the next bus cycle The current bus cycle completes one clock period after TA is asserted synchronous to CLKOUT The number of wait states is determined by the TA input or by the BCR whichever is longer The BCR can be used to set the minimum number of wait states in external bus cycles In order to use the TA functionality the BCR must be programmed to at least one wait sta...

Page 59: ... arbitrator that controls the priority parking and tenure of each master on the same external bus BR is only affected by DSP requests for the external bus never for the internal bus During hardware reset BR is deasserted and the arbitration is reset to the bus slave state BG Input Ignored Input Bus GrantÑBG is an active low input BG must be asserted deasserted synchronous to CLKOUT for proper oper...

Page 60: ...an external pull up resistor CAS Output Tri stated Column Address StrobeÑWhen the DSP is the bus master CAS is an active low output used by DRAM to strobe the column address Otherwise if the Bus Mastership Enable BME bit in the DRAM Control Register is cleared the signal is tri stated BCLK Output Tri stated Bus ClockÑWhen the DSP is the bus master BCLK is an active high output BCLK is active as a ...

Page 61: ... to CLKOUT exact start up timing is guaranteed allowing multiple processors to start synchronously and operate together in lock step When the RESET signal is deasserted the initial chip operating mode is latched from the MODA MODB MODC and MODD inputs The RESET signal must be asserted after power up MODA IRQA Input Input Mode Select AÑMODA is an active low Schmitt trigger input internally synchron...

Page 62: ...s can be resynchronized using the WAIT instruction and asserting IRQB to exit the wait state MODC IRQC Input Input Mode Select CÑMODC is an active low Schmitt trigger input internally synchronized to CLKOUT MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into OMR when the RESET signal is deasserted External Interrupt Request CÑAfter hardware reset this signal becomes ...

Page 63: ...ed as they are in the host port The considerations for proper operation are discussed in Table 2 10 MODD IRQD Input Input Mode Select DÑMODD is an active low Schmitt trigger input internally synchronized to CLKOUT MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into OMR when the RESET signal is deasserted External Interrupt Request DÑAfter hardware reset this signal b...

Page 64: ...rs receive register high RXH receive register middle RXM or receive register low RXL use interrupts or poll the receive register data full RXDF flag which indicates that data is available This assures that the data in the receive byte registers is valid Asynchronous write to transmit byte registers Do not write to the transmit byte registers transmit register high TXH transmit register middle TXM ...

Page 65: ...ort B 0Ð7ÑWhen the HI08 is configured as GPIO through the HPCR these signals are individually programmed as inputs or outputs through the HI08 data direction register HDDR HA0 HAS HAS PB8 Input Input Input or Output Input Host Address Input 0ÑWhen the HI08 is programmed to interface a non multiplexed host bus and the HI function is selected this signal is line 0 of the host address input bus Host ...

Page 66: ...hrough the HPCR this signal is individually programmed as an input or output through the HDDR HA2 HA9 PB10 Input Input Input or Output Input Host Address Input 2ÑWhen the HI08 is programmed to interface a non multiplexed host bus and the HI function is selected this signal is line 2 of the host address HA2 input bus Host Address 9ÑWhen HI08 is programmed to interface a multiplexed host bus and the...

Page 67: ...put or output through the HDDR HDS HDS HWR HWR PB12 Input Input Input or Output Input Host Data StrobeÑWhen HI08 is programmed to interface a single data strobe host bus and the HI function is selected this signal is the host data strobe HDS Schmitt trigger input The polarity of the data strobe is programmable but is configured as active low HDS following reset Host Write DataÑWhen HI08 is program...

Page 68: ...e polarity of the chip select is programmable but is configured active low HCS after reset Host Address 10ÑWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected this signal is line 10 of the host address HA10 input bus Port B 13ÑWhen the HI08 is configured as GPIO through the HPCR this signal is individually programmed as an input or output through the HDDR Ta...

Page 69: ...drain output Transmit Host RequestÑWhen HI08 is programmed to interface a double host request host bus and the HI function is selected this signal is the transmit host request HTRQ output The polarity of the host request is programmable but is configured as active low HTRQ following reset The host request can be programmed as a driven or open drain output Port B 14ÑWhen the HI08 is programmed to i...

Page 70: ...tive low HACK after reset Receive Host RequestÑWhen HI08 is programmed to interface a double host request host bus and the HI function is selected this signal is the receive host request HRRQ output The polarity of the host request is programmable but is configured as active low HRRQ after reset The host request can be programmed as a driven or open drain output Port B 15ÑWhen the HI08 is configur...

Page 71: ...l Interface 0 ESSI0 Signal Name Type State During Reset Signal Description SC00 PC0 Input or Output Input Serial Control 0ÑThe function of SC00 is determined by the selection of either synchronous or asynchronous mode For asynchronous mode this signal is used for the receive clock I O Schmitt trigger input For synchronous mode this signal is used either for Transmitter 1 output or for Serial I O F...

Page 72: ...nal SC01 through PCR0 SC02 PC2 Input Output Input or Output Input Serial Control Signal 2ÑSC02 is used for frame sync I O SC02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode When configured as an output this signal is the internally generated frame sync signal When configured as an input this signal receives an external...

Page 73: ...hases inside each half of the serial clock This signal is driven by a weak keeper after reset Port C 3ÑThe default configuration following reset is GPIO input PC3 When this port is configured as PC3 signal direction is controlled through PRR0 The signal can be configured as an ESSI signal SCK0 through PCR0 SRD0 PC4 Input Output Input or Output Input Serial Receive DataÑSRD0 receives serial data an...

Page 74: ...ta from the serial Transmit shift register STD0 is an output when data is being transmitted This signal is driven by a weak keeper after reset Port C 5ÑThe default configuration following reset is GPIO input PC5 When this port is configured as PC5 signal direction is controlled through PRR0 The signal can be configured as an ESSI signal STD0 through PCR0 Table 2 12 Enhanced Synchronous Serial Inte...

Page 75: ...following reset is GPIO input PD0 When this port is configured as PD0 signal direction is controlled through the Port D direction register PRR1 The signal can be configured as an ESSI signal SC10 through the Port D control register PCR1 SC11 PD1 Input Output Input or Output Input Serial Control 1ÑThe function of this signal is determined by the selection of either synchronous or asynchronous mode ...

Page 76: ...d frame sync signal When configured as an input this signal receives an external frame sync signal for the transmitter The receiver receives an external frame sync signal as well when in synchronous operation This signal is driven by a weak keeper after reset Port D 2ÑThe default configuration following reset is GPIO input PD2 When this port is configured as PD2 signal direction is controlled thro...

Page 77: ...ases inside each half of the serial clock This signal is driven by a weak keeper after reset Port D 3ÑThe default configuration following reset is GPIO input PD3 When this port is configured as PD3 signal direction is controlled through PRR1 The signal can be configured as an ESSI signal SCK1 through PCR1 SRD1 PD4 Input Output Input or Output Input Serial Receive DataÑSRD1 receives serial data and...

Page 78: ... STD1 is an output when data is being transmitted This signal is driven by a weak keeper after reset Port D 5ÑThe default configuration following reset is GPIO input PD5 When this port is configured as PD5 signal direction is controlled through PRR1 The signal can be configured as an ESSI signal STD1 through PCR1 Table 2 13 Enhanced Synchronous Serial Interface 1 ESSI1 Continued Signal Name Type S...

Page 79: ...e shift register This signal is driven by a weak keeper after reset Port E 0ÑThe default configuration following reset is GPIO input PE0 When this port is configured as PE0 signal direction is controlled through the SCI Port E direction register PRR The signal can be configured as an SCI signal RXD through the SCI Port E control register PCR TXD PE1 Output Input or Output Input Serial Transmit Dat...

Page 80: ...listed in Table 2 15 SCLK PE2 Input Output Input or Output Input Serial ClockÑThis is the bidirectional Schmitt trigger input signal providing the input or output clock used by the transmitter and or the receiver This signal is driven by a weak keeper after reset Port E 2ÑThe default configuration following reset is GPIO input PE2 When this port is configured as PE2 signal direction is controlled ...

Page 81: ...per after reset The default mode after reset is GPIO input This can be changed to output or configured as a timer input output through the timer 0 control status register TCSR0 TIO1 Input or Output Input Timer 1 Schmitt Trigger Input OutputÑ When Timer 1 functions as an external event counter or in measurement mode TIO1 is used as input When timer 1 functions in watchdog timer or pulse modulation ...

Page 82: ...reset The default mode after reset is GPIO input This can be changed to output or configured as a timer input output through the timer 2 control status register TCSR2 Table 2 16 OnCE JTAG Interface Signal Name Type State During Reset Signal Description TCK Input Input Test ClockÑTCK is a test clock input signal used to synchronize the JTAG test logic Its pin has a pull up resistor TDI Input Input ...

Page 83: ...ling edge of TCK TMS Input Input Test Mode SelectÑTMS is an input signal used to sequence the test controllerÕs state machine TMS is sampled on the rising edge of TCK and has an internal pull up resistor TRST Input Input Test ResetÑTRST is an active low Schmitt trigger input signal used to asynchronously initialize the test controller TRST has an internal pull up resistor TRST must be asserted aft...

Page 84: ...rmation enter debug mode and wait for commands to be entered from the debug serial input line This signal is asserted as an output for three clock cycles when the chip enters debug mode as a result of a debug request or as a result of meeting a breakpoint condition The DE has an internal pull up resistor This is not a standard part of the JTAG TAP controller The signal connects directly to the OnC...

Page 85: ...2 38 DSP56309UM D MOTOROLA Signal Connection Descriptions OnCE JTAG Interface ...

Page 86: ...MOTOROLA DSP56309UM D 3 1 SECTION 3 MEMORY CONFIGURATION ...

Page 87: ...3 2 DSP56309UM D MOTOROLA Memory Configuration 3 1 MEMORY SPACES 3 3 3 2 RAM CONFIGURATION 3 5 3 3 MEMORY CONFIGURATIONS 3 7 3 4 MEMORY MAPS 3 9 3 5 INTERNAL I O MEMORY MAP 3 18 ...

Page 88: ...fectively using 16 bit program and data words The sixteen bit compatibility mode allows the DSP56309 to use 56000 object code without change thus minimizing system cost for applications that use the smaller address space See the DSP56300 Family Manual for further information 3 1 1 Program Memory Space Program memory space consists of the following Internal program memory Program RAM 20K by default...

Page 89: ...The on chip peripheral registers and some of the DSP56309 core registers occupy the top 128 locations of X data memory FFFF80Ð FFFFFF in the 24 bit Address mode or FF80Ð FFFF in the 16 bit Address mode This area is called X I O space and it can be accessed by MOVE and MOVEP instructions and by bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSET JCLR JSET JSCLR and JSSET For a lis...

Page 90: ... data RAM 7K RAM configuration depends on two bits the Cache Enable CE of the SR and the Memory Select MS of the Operating Mode Register OMR Table 3 1 Memory Space Configuration Bit Settings for the DSP56309 Bit Abbreviation Bit Name Bit Location Cleared 0 Effect Default Set 1 Effect SC Sixteen bit Compatibility SR 13 16M word address space 24 bit address 64K word address space 16 bit address Tabl...

Page 91: ... RAM and Y data RAM can be configured as Program RAM by setting the MS bit When the CE is set the upper 1K of Program RAM is used as an internal Instruction Cache CAUTION While the contents of Program RAM are unaffected by toggling the MS bit the location of program data placed in the Program RAM Instruction Cache area changes after the MS bit is toggled since the cache always occupies the top mos...

Page 92: ...2 4 Bootstrap ROM The bootstrap code is accessed at addresses FF0000 to FFF0BF 192 words in program memory space The bootstrap ROM cannot be accessed in 16 bit address compatibility mode See Appendix AÑBootstrap Programs for a complete listing of the bootstrap code 3 3 MEMORY CONFIGURATIONS Memory configuration determines the size and address range for addressable memory as well as the amount of m...

Page 93: ...pace are determined by the MS and CE bits Their addresses appear in Table 3 5 Table 3 4 RAM Configurations for the DSP56309 Bit Settings Memory Sizes in K MS CE Program RAM X data RAM Y data RAM Cache 0 0 20 7 7 0 0 1 19 7 7 1 1 0 24 5 5 0 1 1 23 5 5 1 Table 3 5 Memory Locations for Program RAM and Instruction Cache MS CE Program RAM Location Cache Location 0 0 0000Ð 4FFF N A 0 1 0000Ð 4BFF 4C00Ð ...

Page 94: ...es appear in Table 3 6 3 4 MEMORY MAPS Figure 3 1 through Figure 3 8 illustrate each of the memory space and RAM configurations defined by the settings of the SC MS and CE bits The figures show the configuration and the accompanying tables show the bit settings memory sizes and memory locations Table 3 6 Memory Locations for Data RAM MS Data RAM Location 0 0000Ð 1BFF 1 0000Ð 13FF ...

Page 95: ...nal Reserved Internal I O External Internal X data RAM 7K External 001C00 Internal Reserved External I O External Internal Y data RAM 7K External FF0000 000000 FFF000 FFFF80 Program X Data Y Data Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 0 0 0 20K 0000Ð 4FFF 7K 0000Ð 1BFF 7K 0000Ð 1BFF None 16M FFFFFF 001C00 FF0000 000000 FFF000 FFFF...

Page 96: ...ed Internal I O External Internal X data RAM 7K External 001C00 Internal Reserved External I O External Internal Y data RAM 7K External FFF000 FFFF80 Program X Data Y Data I Cache 1K 004C00 Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 0 0 1 19K 0000Ð 4BFF 7K 0000Ð 1BFF 7K 0000Ð 1BFF 1K 4C00Ð 4FFF 16 M FFFFFF FF0000 000000 001C00 FFF000 ...

Page 97: ...I O External Internal X data RAM 5K External 001400 Internal Reserved External I O External Internal Y data RAM 5K External FFF000 FFFF80 Program X Data Y Data Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 0 1 0 24K 0000Ð 5FFF 5K 0000Ð 13FF 5K 0000Ð 13FF None 16 M AA0559 External FFFFFF FF0000 000000 001400 FFF000 FFFF80 FFFFFF FF0000 00...

Page 98: ... Internal I O External Internal X data RAM 5K External 001400 Internal Reserved External I O External Internal Y data RAM 5K External FFF000 FFFF80 Program X Data Y Data I Cache 1K 006000 005C00 Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 0 1 1 23K 0000Ð 5BFF 5K 0000Ð 13FF 5K 0000Ð 13FF 1K 5C00Ð 5FFF 16 M Program FFFFFF FF0000 000000 0...

Page 99: ... RAM 20K FFFF 5000 0000 Internal I O Internal X data RAM 7K External External I O Internal Y data RAM 7K External Program X Data Y Data Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 1 0 0 20K 0000Ð 4FFF 7K 0000Ð 1BFF 7K 0000Ð 1BFF None 64K FFFF 0000 FF80 1C00 FFFF 0000 FF80 1C00 ...

Page 100: ...19K FFFF 5000 0000 Internal I O External Internal X data RAM 7K External I O External Internal Y data RAM 7K Program X Data Y Data I Cache 1K 4C00 1C00 Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 1 0 1 19K 0000Ð 4BFF 7K 0000Ð 1BFF 7K 0000Ð 1BFF 1K 4C00Ð 4FFF 64K FFFF 0000 FF80 1C00 FFFF 0000 FF80 ...

Page 101: ... 24K FFFF 0000 Internal I O Internal X data RAM 5K External External I O Internal Y data RAM 5K External FFFF 0000 Program X Data Y Data FF80 1400 6000 Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 1 1 0 24K 0000Ð 5FFF 5K 0000Ð 13FF 5K 0000Ð 13FF None 64K External FFFF 0000 FF80 1400 ...

Page 102: ...ernal I O Internal X data RAM 5K External 1400 External I O Internal Y data RAM 5K External Program X Data Y Data I Cache 1K 6000 5C00 Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 1 1 1 23K 0000Ð 5FFF 5K 0000Ð 13FF 5K 0000Ð 13FF 1K 5C00Ð 5FFF 64K Internal RAM 23K Program FFFF 0000 FF80 1400 FFFF 0000 FF80 ...

Page 103: ...LA Memory Configuration Internal I O Memory Map 3 5 INTERNAL I O MEMORY MAP The DSP56309 internal X I O space the top 128 locations of the X data memory space is listed in Table D 2 on page D 11 of Appendix DÑInterrupt Sources ...

Page 104: ...MOTOROLA DSP56309UM D 4 1 SECTION 4 CORE CONFIGURATION ...

Page 105: ...3 4 3 BOOTSTRAP PROGRAM 4 4 4 4 INTERRUPT SOURCES AND PRIORITIES 4 9 4 5 DMA REQUEST SOURCES 4 16 4 6 OPERATING MODE REGISTER OMR 4 17 4 7 PLL CONTROL REGISTER 4 18 4 8 DEVICE IDENTIFICATION REGISTER IDR 4 18 4 9 AA CONTROL REGISTERS AAR0ÐAAR3 4 19 4 10 JTAG BOUNDARY SCAN REGISTER BSR 4 20 ...

Page 106: ...o one of eight operating modes As the DSP56309 exits the Reset state it loads the values of MODA MODB MODC and MODD into bits MA MB MC and MD of the Operating Mode Register OMR These bit settings select the operating mode which determines the bootstrap program option the microprocessor uses to start up The MAÐMD bits of the OMR can also be set directly by software A jump directly to the bootstrap ...

Page 107: ... 1 Table 4 1 DSP56309 Operating Modes Mode MODD MODC MODB MODA Reset Vector Description 0 0 0 0 0 C00000 Expanded mode address C00000 is reflected as 00000 on Port A signals A0 A17 1 0 0 0 1 FF0000 Reserved 2 0 0 1 0 FF0000 Reserved 3 0 0 1 1 FF0000 Reserved 4 0 1 0 0 FF0000 Reserved 5 0 1 0 1 FF0000 Reserved 6 0 1 1 0 FF0000 Reserved 7 0 1 1 1 FF0000 Reserved 8 1 0 0 0 008000 Expanded mode 9 1 0 ...

Page 108: ...HF0 bit in the host status register HSR causes the DSP56309 to stop loading and begin executing the loaded program at the specified start address See Table 4 1 for a tabular description of the mode bit settings for the operating modes The bootstrap program options except modes 0 and 8 can be invoked at any time by setting the MA MB MC and MD bits in the OMR and jumping to the bootstrap program ent...

Page 109: ...at address C00000 Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected by default 4 3 2 Modes 1 to 7 Reserved These modes are reserved for future use 4 3 3 Mode 8 Expanded Mode The bootstrap ROM is bypassed and the DSP56309 starts fetching instructions beginning at address 008000 Memory accesses are performed using SRAM memory access ty...

Page 110: ...art bit eight data bits one stop bit and no parity Data is received in this order start bit eight data bits LSB first and one stop bit Data is aligned in the SCI receive data register with the LSB of the least significant byte of the received data appearing at bit 0 The user must provide an external clock source with a frequency at least 16 times the transmission data rate Each byte received by th...

Page 111: ...rogram the bootstrap program stops loading instructions jumps to the starting address specified and executes the loaded program 4 3 7 2 Mode D In HC11 Non multiplexed Mode In mode D boot from HI08 in HC11 non multiplexed mode the bootstrap program sets the host interface to interface with the Motorola HC11 microcontroller If the host processor sets host flag 0 HF0 in the HCR while writing the init...

Page 112: ... while writing the initialization program the bootstrap program stops loading instructions jumps to the starting address specified and executes the loaded program 4 4 INTERRUPT SOURCES AND PRIORITIES DSP56309 interrupt handling like that of all DSP56300 family members has been optimized for DSP applications Refer to Section 7 of the DSP56300 Family Manual The interrupt table is located in the 256 ...

Page 113: ... Interrupt Sources Interrupt Starting Address Interrupt Priority Level Range Interrupt Source VBA 00 3 Hardware RESET VBA 02 3 Stack Error VBA 04 3 Illegal Instruction VBA 06 3 Debug Request Interrupt VBA 08 3 Trap VBA 0A 3 Non Maskable Interrupt NMI VBA 0C 3 Reserved VBA 0E 3 Reserved VBA 10 0Ð2 IRQA VBA 12 0Ð2 IRQB VBA 14 0Ð2 IRQC VBA 16 0Ð2 IRQD VBA 18 0Ð2 DMA Channel 0 VBA 1A 0Ð2 DMA Channel 1...

Page 114: ...ESSI1 Receive Last Slot VBA 46 0Ð2 ESSI1 Transmit Data VBA 48 0Ð2 ESSI1 Transmit Data With Exception Status VBA 4A 0Ð2 ESSI1 Transmit Last Slot VBA 4C 0Ð2 Reserved VBA 4E 0Ð2 Reserved VBA 50 0Ð2 SCI Receive Data VBA 52 0Ð2 SCI Receive Data With Exception Status VBA 54 0Ð2 SCI Transmit Data VBA 56 0Ð2 SCI Idle Line VBA 58 0Ð2 SCI Timer VBA 5A 0Ð2 Reserved VBA 5C 0Ð2 Reserved VBA 5E 0Ð2 Reserved VBA...

Page 115: ...t has two interrupt priority level bits IPL 1 0 that determine its interrupt priority level Level 0 is the lowest priority Level 3 is the highest level priority and is non maskable Table 4 3 defines the IPL bits Table 4 3 Interrupt Priority Level Bits IPL bits Interrupts Enabled Interrupts Masked Interrupt Priority Level xxL1 xxL0 0 0 No Ñ 0 0 1 Yes 0 1 1 0 Yes 0 1 2 1 1 Yes 0 1 2 3 ...

Page 116: ...PR C X FFFFFF Figure 4 2 Interrupt Priority Register P IPR P X FFFFFE IAL0 IAL1 IAL2 IBL0 IBL1 IBL2 ICL0 ICL1 ICL2 0 1 2 3 4 5 6 7 8 9 10 11 IRQA IPL IRQA mode IRQB IPL IRQB mode IRQC IPL IRQC mode IRQD IPL D0L0 D0L1 D1L0 D1L1 23 22 21 20 19 18 17 16 15 14 13 12 DMA0 IPL DMA1 IPL D2L0 D2L1 D3L0 D3L1 D4L0 D4L1 D5L0 D5L1 DMA2 IPL DMA3 IPL DMA4 IPL DMA5 IPL IDL2 IDL1 IDL0 IRQD mode HPL0 HPL1 S0L0 S0L...

Page 117: ...e is serviced first This fixed priority list of interrupt sources within an IPL is shown in Table 4 4 Table 4 4 Interrupt Source Priorities within an IPL Priority Interrupt Source Level 3 Nonmaskable Highest Hardware RESET Ñ Stack Error Ñ Illegal Instruction Ñ Debug Request Interrupt Ñ Trap Lowest Non Maskable Interrupt Levels 0 1 2 Maskable Highest IRQA External Interrupt Ñ IRQB External Interrup...

Page 118: ... ESSI0 TX Data Interrupt Ñ ESSI1 RX Data With Exception Interrupt Ñ ESSI1 RX Data Interrupt Ñ ESSI1 Receive Last Slot Interrupt Ñ ESSI1 TX Data With Exception Interrupt Ñ ESSI1 Transmit Last Slot Interrupt Ñ ESSI1 TX Data Interrupt Ñ SCI Receive Data With Exception Interrupt Ñ SCI Receive Data Ñ SCI Transmit Data Ñ SCI Idle Line Ñ SCI Timer Ñ TIMER0 Overflow Interrupt Ñ TIMER0 Compare Interrupt Ñ ...

Page 119: ...owest TIMER2 Compare Interrupt Table 4 5 DMA Request Sources DMA Request Source Bits DRS4 DRS0 Requesting Device 00000 External IRQA signal 00001 External IRQB signal 00010 External IRQC signal 00011 External IRQD signal 00100 Transfer done from DMA channel 0 00101 Transfer done from DMA channel 1 00110 Transfer done from DMA channel 2 00111 Transfer done from DMA channel 3 01000 Transfer done fro...

Page 120: ...M COM 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEN SENWRPEOV EUN XYS ATE APD ABE BRT TAS BE CDP1 0 MS SD EBD MD MC MB MA PENÑPatch Enable ATEÑAddress Tracing Enable MSÑMemory Switch Mode SENÑStack Extension Enable APDÑAddress Priority Disable SDÑStop Delay WRPÑExtended Stack Wrap Flag ABEÑAsynch Bus Arbitration Enable EBDÑExternal Bus Disable EOVÑExtended Stack Overflow Flag B...

Page 121: ... chip crystal oscillator XTAL output The XTLD bit is cleared during a DSP56309 hardware reset which means that the XTAL output signal is active permitting normal operation of the crystal oscillator 4 7 3 PCTL Predivider Factor Bits PD0ÐPD3 Bits 20Ð23 The predivider factor bits PD0ÐPD3 define the predivision factor PDF to be applied to the PLL input frequency The PD0ÐPD3 bits are cleared during a D...

Page 122: ...ivative number and revision number of that device Figure 4 5 Identification Register Configuration Revision 0 4 9 AA CONTROL REGISTERS AAR0ÐAAR3 The address attribute register AAR appears in Figure 4 6 There are four of these registers in the DSP56309 AAR0ÐAAR3 one for each AA signal For a full description of the address attribute registers see the DSP56300 Family Manual Address multiplexing is no...

Page 123: ...the BSR The BSR is documented in Section 11 5ÑDSP56309 Boundary Scan Register on page 11 13 The JTAG code is listed in Appendix CÑDSP56309 BSDL Listing Figure 4 6 Address Attribute Registers AAR0ÐAAR3 X FFFFF9Ð FFFFF6 BAC0 BPEN 0 1 BYEN 2 BAT1 3 BAAP 4 5 6 7 8 9 10 11 BXEN 12 13 14 BAC8 15 16 17 18 19 20 21 22 23 BAT0 BAC3 BAC2 BAC11 BAC5 BAC7 BAC6 BAC9 BAC10 BAC1 BNC3 BNC1 BNC2 BNC0 BAC4 BPAC Res...

Page 124: ...MOTOROLA DSP56309UM D 5 1 SECTION 5 GENERAL PURPOSE I O ...

Page 125: ...5 2 DSP56309UM D MOTOROLA General Purpose I O 5 1 INTRODUCTION 5 3 5 2 PROGRAMMING MODEL 5 3 ...

Page 126: ...he HI08 signals Port C six GPIO signals shared with the ESSI0 signals Port D six GPIO signals shared with the ESSI1 signals Port E three GPIO signals shared with the SCI signals Timers three GPIO signals shared with the Triple Timer signals 5 2 1 Port B Signals and Registers Each of the 16 Port B signals not used as a HI08 signal can be configured as a GPIO signal The GPIO functionality of Port B ...

Page 127: ...als and Registers Each of the three Port E signals not used as a SCI signal can be configured as a GPIO signal The GPIO functionality of Port E is controlled by three registers Port E control register PCRE Port E direction register PRRE and Port E data register PDRE These registers are documented in Section 8ÑSerial Communication Interface SCI of this manual 5 2 5 Triple Timer Signals Each of the ...

Page 128: ...MOTOROLA DSP56309UM D 6 1 SECTION 6 HOST INTERFACE HI08 ...

Page 129: ...ION 6 3 6 2 HI08 FEATURES 6 3 6 3 HI08 HOST PORT SIGNALS 6 6 6 4 HI08 BLOCK DIAGRAM 6 7 6 5 HI08 DSP SIDE PROGRAMMERÕS MODEL 6 8 6 6 HI08 EXTERNAL HOST PROGRAMMERÕS MODEL 6 20 6 7 SERVICING THE HOST INTERFACE 6 31 6 8 HI08 PROGRAMMING MODEL QUICK REFERENCE 6 34 ...

Page 130: ...ister bank is accessible to the DSP core The HI08 supports two classes of interfaces Host Processor Microcontroller MCU connection interface GPIO port Signals not used as HI08 port signals can be configured as GPIO signals up to a total of 16 6 2 HI08 FEATURES This section lists the features of the host to DSP and DSP to host interfaces Further details are given in Section 6 5ÑHI08 DSP Side Progra...

Page 131: ... multiplexed or multiplexed buses Ð H0ÐH7 HAD0ÐHAD7 host data bus H0ÐH7 or host multiplexed address data bus HAD0ÐHAD7 Ð HAS HA0 address strobe HAS or host address line HA0 Ð HA8 HA1 host address line HA8 or host address line HA1 Ð HA9 HA2 host address line HA9 or host address line HA2 Ð HRW HRD read write select HRW or read strobe HRD Ð HDS HWR data strobe HDS or write strobe HWR Ð HCS HA10 host ...

Page 132: ...s Ð Separate interrupt lines for each interrupt source Ð Special host commands force DSP core interrupts under host processor control These commands are useful for these purposes Real time production diagnostics Creating a debugging window for program development Host control protocols Interface capabilities Ð Glueless interface no external logic required to these devices Motorola HC11 Hitachi H8 ...

Page 133: ...rational Modes HI08 Port Signal Multiplexed Address Data Bus Mode Non Multiplexed Bus Mode GPIO Mode HAD0ÐHAD7 HAD0ÐHAD7 H0ÐH7 PB0ÐPB7 HAS HA0 HAS HAS HA0 PB8 HA8 HA1 HA8 HA1 PB9 HA9 HA2 HA9 HA2 PB10 HCS HA10 HA10 HCS HCS PB13 Table 6 2 HI08 Data Strobe Signals HI08 Port Signal Single Strobe Bus Dual Strobe Bus GPIO Mode HRW HRD HRW HRD HRD PB11 HDS HWR HDS HDS HWR HWR PB12 Table 6 3 HI08 Host Req...

Page 134: ...Data Bus RXH HCR Host Control Register HSR Host Status Register HPCR Host Port Control Register HBAR Host Base Address register HTX Host Transmit register HRX Host Receive register HDDR Host Data Direction Register HDR Host Data Register ICR Interface Control Register CVR Command Vector Register ISR Interface Status Register IVR Interrupt Vector Register RXH Receive Register High RXM Receive Regis...

Page 135: ...rol with eight registers in all All eight registers can be accessed by the DSP core but not by the external host Data registers are 24 bit registers used for high speed data transfer to and from the DSP Host data receive register HRX Host data transmit register HTX The DSP side control registers are 16 bit registers that control DSP functions The eight MSBs in the DSP side control registers are re...

Page 136: ...ta full ISR RXDF bits are cleared This transfer operation sets the HTDE and RXDF bits The DSP56309 sets the HTIE bit to cause a host transmit data interrupt when HTDE is set To prevent the previous data from being overwritten data should not be written to the HTX until the HTDE bit is set Note During data writes to a peripheral device there is a two cycle pipeline delay until any status bits affec...

Page 137: ...upts are disabled The interrupt address is determined by the host command vector register CVR Note If more than one interrupt request source is asserted and enabled e g HRDF is set HCP is set HRIE is set and HCIE is set the HI08 generates interrupt requests according to priorities shown in Table 6 4 6 5 3 4 HCR Host Flags 2 3 HF 3 2 Bits 3 4 HF 3 2 bits are general purpose flags for DSP to host co...

Page 138: ...erred to the RXH RXM RXL registers HTDE is also set when the host processor uses the initialize function If HTDE is set the HI08 generates a transmit data full DMA request HTDE is cleared when HTX is written by the DSP core 6 5 4 3 HSR Host Command Pending HCP Bit 2 The HCP bit indicates that the host has set the HC bit and that a host command interrupt is pending The HCP bit reflects the status o...

Page 139: ...here the host side registers are mapped into the bus address space 6 5 5 2 HBAR Reserved Bits 8 15 These bits are reserved They are read as 0 and should be written with 0 6 5 6 Host Port Control Register HPCR The HPCR is a 16 bit read write control register by which the DSP controls the HI08 operating mode Reserved bits are read as 0 and should be written with 0 for future compatibility The initia...

Page 140: ...en HA8 HA1 acts as a GPIO signal according to the value of the HDDR and HDR Note HA8EN is ignored when the HI08 is not in the multiplexed bus mode HMUX is cleared 6 5 6 3 HPCR Host Address Line 9 Enable HA9EN Bit 2 If HA9EN is set and the HI08 is in multiplexed bus mode then HA9 HA2 acts as host address line 9 HA9 If this bit is cleared and the HI08 is in multiplexed bus mode then HA9 HA2 is confi...

Page 141: ...ignored 6 5 6 7 HPCR Host Enable HEN Bit 6 If HEN is set the HI08 operates as the host interface If HEN is cleared the HI08 is not active and all the HI08 signals are configured as GPIO signals according to the value of the HDDR and HDR 6 5 6 8 HPCR Reserved Bit 7 This bit is reserved It is read as 0 and should be written as 0 6 5 6 9 HPCR Host Request Open Drain HROD Bit 8 The HROD bit controls t...

Page 142: ... host registers are taken from the internal latch If HMUX is cleared it indicates that the HI08 is connected to a non multiplexed type of bus The values of the address lines are then taken from the HI08 input signals 6 5 6 13 HPCR Host Dual Data Strobe HDDS Bit 12 If the HDDS bit is cleared the HI08 operates in the single strobe bus mode In this mode the bus has a single data strobe signal for bot...

Page 143: ...led the HREQ signal is an active high output In the double host request mode HDRQ is set in the ICR if HRP is cleared and host requests are enabled HREN is set and HEN is set the HTRQ and HRRQ signals are active low outputs If HRP is set and host requests are enabled the HTRQ and HRRQ signals are active high outputs 6 5 6 16 HPCR Host Acknowledge Polarity HAP Bit 15 If the HAP bit is cleared the h...

Page 144: ...n output signal If bit DRxx is cleared the corresponding HI08 signal is configured as an input signal 6 5 8 Host Data Register HDR The HDR register holds the data value of the corresponding bits of the HI08 signals configured as GPIO signals It is illustrated in Figure 6 10 The functionality of the Dxx bit depends on the corresponding HDDR bit DRxx as in Table 6 5 The HDR cannot be accessed by the...

Page 145: ...dual reset IR Ñcaused by clearing the HPCR HEN Stop reset ST Ñcaused by executing the STOP instruction Table 6 5 HDR and HDDR Functionality HDDR HDR DRxx Dxx Configured as GPIO signal Configured as non GPIO signal 0 Read only bitÑ The value read is the binary value of the signal The corresponding signal is configured as an input Read only bitÑDoes not contain significant data 1 Read write bitÑ The...

Page 146: ...pts caused by the host processor by jumping to the appropriate interrupt service routine There are three possible interrupts Host command Transmit data register empty Receive data register full Although there is a set of vectors reserved for host command use the host command can access any interrupt vector in the interrupt vector table The DSP interrupt service Table 6 6 DSP Side Registers after R...

Page 147: ...s are double buffered to allow the DSP core and host processor to transfer data efficiently at high speed The host can access the HI08 asynchronously by using polling techniques or interrupt based techniques The HI08 appears to the host processor as a memory mapped peripheral occupying eight bytes in the host processor address space as in Table 6 7 on page 6 22 The eight HI08 registers include the...

Page 148: ...can be transferred between the host processor and the DSP56309 at the fastest host processor data rate One of the most innovative features of the host interface is the host command feature With this feature the host processor can issue vectored interrupt requests to the DSP56309 The host can select any of 128 DSP interrupt routines for execution by writing a vector address register in the HI08 Thi...

Page 149: ... on control register bits The control bits are described in the following paragraphs Table 6 7 Host Side Register Map Host Address Big Endian HLEND 0 Little Endian HLEND 1 0 ICR ICR Interface Control 1 CVR CVR Command Vector 2 ISR ISR Interface Status 3 IVR IVR Interrupt Vector 4 00000000 00000000 Unused 5 RXH TXH RXL TXL Receive Transmit Bytes 6 RXM TXM RXM TXM 7 RXL TXL RXH TXH Host Data Bus H0 ...

Page 150: ...REQ is cleared TXDE interrupts are disabled If TREQ and TXDE are set the host request signal is asserted Table 6 8 and Table 6 9 summarize the effect of RREQ and TREQ on the HREQ and HRRQ signals 6 6 1 3 ICR Double Host Request HDRQ Bit 2 If cleared the HDRQ bit configures HREQ HTRQ and HACK HRRQ as HREQ and HACK respectively If HDRQ is set HREQ HTRQ and HACK HRRQ are configured as HTRQ and HRRQ r...

Page 151: ...LEND bit is cleared the host can access the HI08 in big endian byte order If set the host can access the HI08 in little endian byte order If the HLEND bit is cleared the RXH TXH register is located at address 5 the RXM TXM register at 6 and the RXL TXL register at 7 If the HLEND bit is set the RXH TXH register is located at address 7 the RXM TXM register at 6 and the RXL TXL register at 5 6 6 1 7 ...

Page 152: ...ore to be executed This register is illustrated in Figure 6 13 6 6 2 1 CVR Host Vector HV 6 0 Bits 0Ð6 The seven HV bits select the host command interrupt address to be used by the host command interrupt logic When the host command interrupt is recognized by the DSP interrupt control logic the address of the interrupt routine taken is 2 HV The host can write HC and HV in the same write cycle The h...

Page 153: ...interface status register ISR is an 8 bit read only status register used by the host processor to interrogate the status and flags of the HI08 The host processor can write to this address without affecting the internal state of the HI08 The DSP core cannot access the ISR The ISR bits are described in the following paragraphs This register is illustrated in Figure 6 14 6 6 3 1 ISR Receive Data Regi...

Page 154: ...TXM TXL is immediately transferred to the DSP side of the HI08 This feature has many applications For example if the host processor issues a host command which causes the DSP56309 to read the HRX the host processor can be guaranteed that the data it just transferred to the HI08 is that being received by the DSP56309 6 6 3 4 ISR Host Flag 2 HF2 Bit 3 HF2 indicates the state of host flag 2 in the HC...

Page 155: ...VR are placed on the host data bus H 7 0 when both the HREQ and HACK signals are asserted The contents of this register are initialized to 0F by a hardware RESET signal or software RESET instruction This value corresponds to the uninitialized interrupt vector in the MC68000 family This register is illustrated in Figure 6 15 6 6 5 Receive Byte Registers RXH RXM RXL The receive byte registers are vi...

Page 156: ...transmit high register TXH the transmit middle register TXM and the transmit low register TXL These registers send data to the high middle and low bytes respectively of the HRX register and are selected by the external host address inputs HA 2 0 during a host processor write operation If the HLEND bit in the ICR is set the TXH register is located at address 7 the TXM register at 6 and the TXL regi...

Page 157: ... viewed by the DSP56309 as memory mapped registers as documented in Section 6 5ÑHI08 DSP Side ProgrammerÕs Model on page 6 8 Those memory mapped registers control up to 16 I O signals Software RESET instructions and hardware RESET signals clear all DSP side control registers and configure the HI08 as GPIO with all 16 signals disconnected External circuitry Table 6 12 Host Side Registers After Rese...

Page 158: ...ollowing protocols Polling Interrupts The host processor writes to the appropriate HI08 register to reset the control bits and configure the HI08 for proper operation 6 7 1 HI08 Host Processor Data Transfer To the host processor the HI08 looks like a contiguous block of Static RAM To transfer data between itself and the HI08 the host processor performs the following steps 1 asserts the HI08 addres...

Page 159: ...tate within the DSP56309 has been reached Intervention by the host processor may be required If HREQ is set the HREQ TRQ signal has been asserted and the DSP56309 is requesting the attention of the host processor One of the previous four conditions exists After the appropriate data transfer has been made the corresponding status bit is updated to reflect the transfer If the host processor has issu...

Page 160: ... DSP is reset If the host processor is a member of the MC68000 family there is no need for the additional step when the host processor reads the ISR to determine how to respond to an interrupt generated by the DSP56309 Instead the DSP56309 automatically sources the contents of the IVR on the data bus when the host processor acknowledges the interrupt by asserting HACK The contents of the IVR are p...

Page 161: ... Ñ 0 Ñ Ñ 2 HCIE Host Command Interrupt Enable 0 1 HCP interrupt disabled HCP interrupt enabled Ñ 0 Ñ Ñ 3 HF2 Host Flag 2 Ñ Ñ Ñ 0 Ñ Ñ 4 HF3 Host Flag 3 Ñ Ñ Ñ 0 Ñ Ñ HPCR 0 HGEN Host GPIO Enable 0 1 GPIO signal disconnected GPIO signals active Ñ 0 Ñ Ñ 1 HA8EN Host Address Line 8 Enable 0 1 HA8 A1 GPIO HA8 A1 HA8 This bit is treated as 1 if HMUX 0 This bit is treated as 0 if HEN 0 0 Ñ Ñ 2 HA9EN Host A...

Page 162: ...t Active Ñ 0 Ñ Ñ 8 HROD Host Request Open Drain 0 1 HREQ HTRQ HRRQ driven HREQ HTRQ HRRQ open drain This bit is ignored if HEN 0 0 9 HDSP Host Data Strobe Polarity 0 1 HDS HRD HWR active low HDS HRD HWR active high This bit is ignored if HEN 0 0 Ñ Ñ 10 HASP Host Address Strobe Polarity 0 1 HAS active low HAS active high This bit is ignored if HEN 0 0 Ñ Ñ 11 HMUX Host Multiplexed Bus 0 1 Separate a...

Page 163: ...ve Data Register is full Ñ 0 0 0 1 HTDE Host Transmit Data Empty 1 0 The Transmit Data Register is empty The Transmit Data Register is not empty Ñ 1 1 1 2 HCP Host Command Pending 0 1 no host command pending host command pending Ñ 0 0 0 3 HF0 Host Flag 0 Ñ Ñ Ñ 0 Ñ Ñ 4 HF1 Host Flag 1 Ñ Ñ Ñ 0 Ñ Ñ HBAR 7 0 BA10 BA3 Host Base Address Register Ñ Ñ Ñ 80 Ñ Ñ HRX 23 0 Ñ DSP Receive Data Register Ñ Ñ Ñ em...

Page 164: ...t enabled Ñ 0 Ñ Ñ 2 HDRQ Double Host Request 0 1 HREQ HTRQ HREQ HACK HRRQ HACK HREQ HTRQ HTRQ HACK HRRQ HRRQ Ñ 0 Ñ Ñ 3 HF0 Host Flag 0 Ñ Ñ Ñ 0 Ñ Ñ 4 HF1 Host Flag 1 Ñ Ñ Ñ 0 Ñ Ñ 5 HLEND Host Little Endian 0 1 Big Endian order Little Endian order Ñ 0 Ñ Ñ 7 INIT Initialize 1 Reset data paths according to TREQ and RREQ cleared by HI08 hardware 0 Ñ Ñ Table 6 13 HI08 Programming Model Continued Reg Bit ...

Page 165: ...st Flag 3 Ñ Ñ Ñ 0 Ñ Ñ 7 HREQ Host Request 0 1 HREQ signal is deasserted HREQ signal is asserted if enabled Ñ 0 0 0 CVR 6 0 HV6 HV0 Host Command Vector Ñ Ñ default vector via programmable 32 Ñ Ñ CVR 7 HC Host Command 0 1 no host command pending host command pending cleared by HI08 hardware when the HC interrupt request is serviced 0 0 0 RXH M L 7 0 Ñ Host Receive Data Register Ñ Ñ Ñ empty Ñ Ñ TXH M...

Page 166: ...MOTOROLA DSP56309UM D 7 1 SECTION 7 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI ...

Page 167: ... Enhanced Synchronous Serial Interface ESSI 7 1 INTRODUCTION 7 3 7 2 ENHANCEMENTS TO THE ESSI 7 3 7 3 ESSI DATA AND CONTROL SIGNALS 7 4 7 4 ESSI PROGRAMMING MODEL 7 8 7 5 OPERATING MODES 7 36 7 6 GPIO SIGNALS AND REGISTERS 7 43 ...

Page 168: ...device because all transfers are synchronized to these clocks Additional synchronization signals are used to delineate the word frames Normal mode is used to transfer data at a periodic rate one word per period Network mode is similar in that it is also intended for periodic transfers however it supports up to 32 words time slots per period Network mode can be used to build time division multiplex...

Page 169: ...they are programmed as transmit data signals 7 3 1 Serial Transmit Data STD Signal The STD signal is used for transmitting data from the TX0 serial transmit shift register STD is an output when data is being transmitted from the TX0 shift register With an internally generated bit clock the STD signal becomes a high impedance output signal for a full clock period after the last data bit has been tr...

Page 170: ...terface The SCK signal is a clock input or output used by all the enabled transmitters and receiver in synchronous modes or by all the enabled transmitters in asynchronous Figure 7 1 ESSI Block Diagram RSMA RSMB TSMA TSMB SSISR RX RX SHIFT REG TX0 SHIFT REG TSR RCLK TX0 CRB CRA SRD STD TCLK SC2 SCK Clock Frame Sync Generators and Control Logic Interrupts GDB DDB TX1 SHIFT REG TX1 SC0 TX2 SHIFT REG...

Page 171: ...e this signal is used as the transmitter data out signal for transmit shift register 1 or for serial flag I O A typical application of serial flag I O would be multiple device selection for addressing in codec systems If SC0 is configured as a serial flag signal its direction is determined by the serial control direction 0 SCD0 bit in the ESSI control register B CRB When configured as an output it...

Page 172: ...ther for multiple serial device selection SC0 and SC1 can be used unencoded to select up to two codecs or can be decoded externally to select up to four codecs If SC1 is configured as a serial flag signal its direction is determined by the SCD1 bit in the CRB When configured as an output its value is determined by the value of the serial output flag1 OF1 bit in the CRB When configured as an input ...

Page 173: ...rnally generated frame sync signal When configured as an input this signal receives an external frame sync signal for the transmitter in asynchronous mode and for the receiver when in synchronous mode SC2 can be programmed as a GPIO signal P2 when the ESSI SC2 function is not being used 7 4 ESSI PROGRAMMING MODEL The ESSI includes the following registers Two control registers CRA CRB illustrated i...

Page 174: ... the ESSI is documented in Section 7 6ÑGPIO Signals and Registers of this manual 11 10 9 8 7 6 5 4 3 2 1 0 PSR PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 23 22 21 20 19 18 17 16 15 14 13 12 SSC1 WL2 WL1 WL0 ALC DC4 DC3 DC2 DC1 DC0 AA0857 Figure 7 2 ESSI Control Register A CRA ESSI0 X FFFFB5 ESSI1 X FFFFA5 11 10 9 8 7 6 5 4 3 2 1 0 CKP FSP FSR FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0 OF1 OF0 23 22 21 20 19 18 17 16...

Page 175: ...TS31 TS30 TS29 TS28 AA0861 Figure 7 6 ESSI Transmit Slot Mask Register B TSMB ESSI0 X FFFFB3 ESSI1 X FFFFA3 11 10 9 8 7 6 5 4 3 2 1 0 RS11 RS10 RS9 RS8 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 23 22 21 20 19 18 17 16 15 14 13 12 RS15 RS14 RS13 RS12 AA0862 Figure 7 7 ESSI Receive Slot Mask Register A RSMA ESSI0 X FFFFB2 ESSI1 X FFFFA2 11 10 9 8 7 6 5 4 3 2 1 0 RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS...

Page 176: ...re clock frequency the same frequency as the CLKOUT signal when that signal is enabled Careful choice of the crystal oscillator frequency and the prescaler modulus allows generation of the industry standard codec master clock frequencies of 2 048 MHz 1 544 MHz and 1 536 MHz Both the hardware RESET signal and the software RESET instruction clear PM 7 0 7 4 1 2 CRA Reserved Bits 8Ð10 These bits are ...

Page 177: ...tio of one DC 00000 provides continuous periodic data word transfers A bit length frame sync must be used in this case and is selected by setting the FSL 1 0 bits in the CRA to 01 Both the hardware RESET signal and the software RESET instruction clear DC 4 0 The ESSI frame sync generator functional diagram is shown in Figure 7 10 Figure 7 9 ESSI Clock Generator Functional Block Diagram SCn0 SCKn C...

Page 178: ...ift register Transmitted words must be left aligned to bit 23 in the transmit shift register The ALC bit is cleared by either a hardware RESET signal or a software RESET instruction Note If the ALC bit is set only 8 12 or 16 bit words should be used The use of 24 or 32 bit words leads to unpredictable results Figure 7 10 ESSI Frame Sync Generator Functional Block Diagram Frame Sync Transmit Frame ...

Page 179: ...ared by a hardware RESET signal or by a software RESET instruction 7 4 1 8 CRA Select SC1 SSC1 Bit 22 The SSC1 bit controls the functionality of the SC1 signal This bit is only valid when the ESSI is configured in synchronous mode i e if the CRB synchronous asynchronous bit SYN is set and transmitter 2 is disabled i e if transmit enable TE2 0 If SSC1 is set and SC1 is configured as an output SCD1 ...

Page 180: ...4 on page 7 24 The ESSI CRB bits are described in the following paragraphs 7 4 2 1 CRB Serial Output Flags OF0 OF1 Bits 0 1 The ESSI has two serial output flag bits OF1 and OF0 The normal sequence for setting output flags when transmitting data by transmitter 0 through the STD signal only consists of these steps 1 Wait for TDE TX0 empty to be set 2 Write the flags 3 Write the transmit data to the ...

Page 181: ... mode SYN 1 when transmitter 2 is disabled TE2 0 or in asynchronous mode SYN 0 SCD1 controls the direction of the SC1 I O signal When SCD1 is set SC1 is an output when SCD1 is cleared SC1 is an input When TE2 is set the value of SCD1 is ignored and the SC1 signal is always an output Bit SCD1 is cleared by a hardware RESET signal or by a software RESET instruction 7 4 2 4 CRB Serial Control Directi...

Page 182: ...able 7 3 The word length is defined by WL 2 0 Either a hardware RESET signal or a software RESET instruction clears FSL 1 0 7 4 2 8 CRB Frame Sync Relative Timing FSR Bit 9 The FSR bit determines the relative timing of the receive and transmit frame sync signal in reference to the serial data lines for word length frame sync only When FSR is cleared the word length frame sync occurs together with ...

Page 183: ...et the data and the frame sync are clocked out on the falling edge of the transmit bit clock and latched in on the rising edge of the receive bit clock Either a hardware RESET signal or a software RESET instruction clears CKP 7 4 2 11 CRB Synchronous Asynchronous SYN Bit 12 SYN controls whether the receive and transmit functions of the ESSI occur synchronously or asynchronously with respect to eac...

Page 184: ...ccurs while data is valid Data Data Serial Clock RX TX Frame SYNC One Bit Length FSL1 1 FSL0 0 RX TX Serial Data NOTE Frame sync occurs for one bit time preceding the data Serial Clock TX Frame SYNC Mixed Frame Length FSL1 0 FSL0 1 RX Frame Sync Serial Clock TX Frame SYNC Mixed Frame Length FSL1 1 FSL0 1 TX Serial Data RX Frame SYNC Data Data Data Data Data Data Data Data Data Data RXSerial Data T...

Page 185: ...y time slot For more details see Section 7 5ÑOperating Modes Either a hardware RESET signal or a software RESET instruction clears MOD Figure 7 12 CRB SYN Bit Operation External Frame SYNC SC1 Asynchronous SYN 0 Transmitter Clock Frame SYNC RECEIVER Clock Frame SYNC SRD STD SC2 External Transmit Frame SYNC External Receive Frame SYNC Internal Frame SYNC SC0 SC External Transmit Clock External Rece...

Page 186: ... Transmitter Interrupt or DMA Request and Flags Set Receiver Interrupt or DMA Request and Flags Set NOTE Interrupts occur and data is transferred once per frame sync Network Mode MOD 1 Serial Clock Frame SYNC Transmitter Interrupts or DMA Request and Flags Set Slot 1 Slot 2 Slot 3 Slot 1 Slot 2 Serial Data Receiver Interrupt or DMA Request and Flags Set NOTE Interrupts occur every time slot and a ...

Page 187: ...n of the current data word The transmitter remains disabled until the beginning of the next frame During that time period the corresponding SC or STD in the case of TX0 signal remains in the high impedance state 7 4 2 14 CRB ESSI Transmit 2 Enable TE2 Bit 14 The TE2 bit enables the transfer of data from TX2 to transmit shift register 2 TE2 is functional only when the ESSI is in synchronous mode an...

Page 188: ...SI is in synchronous mode and is ignored when the ESSI is in asynchronous mode When TE1 is set and a frame sync is detected the transmitter 1 is enabled for that frame When TE1 is cleared transmitter 1 is disabled after completing transmission of data currently in the ESSI transmit shift register Any data present in TX1 is not transmitted If TE1 is cleared data can be written to TX1 the TDE bit is...

Page 189: ...utput is tri stated and any data present in TX0 is not transmitted i e data can be written to TX0 with TE0 cleared the TDE bit is cleared but data is not transferred to the transmit shift register 0 The TE0 bit is cleared by either a hardware RESET signal or a software RESET instruction The transmit enable sequence for on demand mode can be the same as for normal mode or TE0 can be left enabled No...

Page 190: ...D U FS XC TD0 RD 1 1 1 1 0 TD1 TD2 FS XC TD0 U 1 1 1 1 1 TD1 TD2 FS XC TD0 RD Note TXC Transmitter Clock Note RXC Receiver Clock Note XC Transmitter Receiver Clock Synchronous Operation Note FST Transmitter Frame Sync Note FSR Receiver Frame Sync Note FS Transmitter Receiver Frame Sync Synchronous Operation Note TD0 Transmit Data signal 0 Note TD1 Transmit Data signal 1 Note TD2 Transmit Data sign...

Page 191: ...rrupt Transmit interrupts with exception conditions have higher priority than normal transmit data interrupts If the transmitter underrun error TUE bit is set signaling that an exception has occurred and the TEIE bit is set the ESSI requests an SSI transmit data with exception interrupt from the interrupt controller TIE is cleared by either a hardware RESET signal or a software RESET instruction 7...

Page 192: ...e TEIE Bit 22 When the TEIE bit is set the DSP is interrupted when both TDE and TUE in the ESSI Status Register are set When TEIE is cleared this interrupt is disabled The use of the transmit interrupt is described in Section 7 5 3ÑESSI Exceptions Reading the status register followed by writing to all the data registers of the enabled transmitters clears both TUE and the pending interrupt TEIE is ...

Page 193: ...data in the receive shift register is transferred into the receive data register If it is not enabled the IF1 bit is cleared A hardware RESET signal software RESET instruction ESSI individual reset or STOP instruction clears the IF1 bit 7 4 3 3 SSISR Transmit Frame Sync Flag TFS Bit 2 When set TFS indicates that a transmit frame sync occurred in the current time slot TFS is set at the start of the...

Page 194: ...o be cleared by first reading the SSISR with the TUE bit set then writing to all the enabled transmit data registers or to the TSR 7 4 3 6 SSISR Receiver Overrun Error Flag ROE Bit 5 The ROE bit is set when the serial receive shift register is filled and ready to transfer to the receive data register RX but RX is already full i e the RDF bit is set If the REIE bit is set a DSP receiver overrun err...

Page 195: ...er are transferred to the receive data register The RDF bit is cleared when the DSP reads the receive data register If RIE is set a DSP receive data interrupt request is issued when RDF is set A hardware RESET signal software RESET instruction ESSI individual reset or STOP instruction clears the RDF bit The ESSI data path programming models are shown in Figure 7 16 on page 7 31 and Figure 7 17 on ...

Page 196: ...isters STD ESSI Transmit Data Register Write Only ESSI Transmit Shift Register 24 bit Data 0 0 0 16 bit Data 12 bit Data 8 bit Data LSB LSB LSB LSB Least Significant Zero Fill b Transmit Registers Transmit High Byte Transmit Middle Byte Transmit Low Byte Transmit High Byte Transmit Middle Byte Transmit Low Byte 23 16 15 8 7 0 23 16 15 8 7 0 7 0 7 0 7 0 7 0 7 0 7 0 MSB MSB MSB NOTES Data is transmi...

Page 197: ...a 12 bit Data 8 bit Data LSB LSB LSB LSB MSB MSB MSB MSB Least Significant Zero Fill 16 Bit 12 Bit 8 Bit b Transmit Registers Receive High Byte Receive Middle Byte Receive Low Byte Receive High Byte Receive Middle Byte Receive Low Byte 23 16 15 8 7 0 23 16 15 7 0 7 0 7 7 0 7 0 7 0 7 0 NOTES Data is received MSB first if SHFD 0 24 bit fractional format ALC 0 32 bit mode is not shown Transmit High B...

Page 198: ...ignificant byte is unused When the ALC bit is set the MSB is bit 15 and the most significant byte is unused Unused bits are read as 0s If the associated interrupt is enabled the DSP is interrupted whenever the RX register becomes full 7 4 6 ESSI Transmit Shift Registers The three 24 bit transmit shift registers contain the data being transmitted see Figure 7 16 on page 7 31 and Figure 7 17 on page...

Page 199: ...If you read any of those status bits within the next two cycles the bit does not reflect its current status See the DSP56300 Family Manual Appendix B Polling a Peripheral Device for Write for further details 7 4 8 ESSI Time Slot Register TSR TSR is effectively a write only null data register that is used to prevent data transmission in the current transmit time slot For the purposes of timing TSR ...

Page 200: ...me currently being transmitted is not affected by the new TSM setting If the TSM is read it shows the current setting After a hardware RESET signal or software RESET instruction the TSM register is reset to FFFFFFFF this setting enables all thirty two slots for data transmission 7 4 10 Receive Slot Mask Registers RSMA RSMB The receive slot mask registers are two 16 bit read write registers In netw...

Page 201: ...eset state while all ESSI signals are programmed as GPIO the ESSI is active only if at least one of the ESSI I O signals is programmed as an ESSI signal 7 5 2 ESSI Initialization To initialize the ESSI do the following 1 Send a reset a hardware RESET signal software RESET instruction ESSI individual reset or STOP instruction 2 Program the ESSI control and time slot registers 3 Write data to all th...

Page 202: ...ed even if DMA is used to service the transmitters 5 Enable the transmitters and receiver to be used Now the ESSI can be serviced by polling interrupts or DMA Once the ESSI has been enabled Step 3 operation starts as follows For internally generated clock and frame sync these signals start activity immediately after the ESSI is enabled Data is received by the ESSI after the occurrence of a frame s...

Page 203: ...e enabled transmitters is empty and a transmitter underrun error has occurred This exception sets the TUE bit The TUE bit is cleared by first reading the SSISR and then writing to all the transmit data registers of the enabled transmitters or by writing to the TSR to clear the pending interrupt 5 ESSI transmit last slot interrupt Occurs when the ESSI is in network mode at the start of the last slo...

Page 204: ...ight of the steps above shows register settings for configuring an ESSI0 transmit interrupt using transmitter 0 2 The order of the steps is optional except that the interrupt trigger configuration must not be completed until the ISR configuration has been completed Since 2d can cause an immediate transmit without generating an interrupt perform the transmit data preload in 2c before 2d to insure v...

Page 205: ...A frame sync pulse is generated only when data is available to transmit The frame sync signal indicates the first time slot in the frame The on demand mode requires that the transmit frame sync be internal output and the receive frame sync be external input For simplex operation synchronous mode could be used however for full duplex operation asynchronous mode must be used Data transmission that i...

Page 206: ... is asserted during the entire data transfer period This frame sync length is compatible with Motorola codecs serial peripherals that conform to the Motorola SPI serial A D and D A converters shift registers and telecommunication pulse code modulation PCM serial I O If the FSL1 bit is set the RX frame sync pulses active for one bit clock immediately before the data transfer period This frame sync ...

Page 207: ... not recognized and the receiver is internally disabled until the next frame sync Frames do not have to be adjacent that is a new frame sync does not have to follow immediately the previous frame Gaps of arbitrary periods can occur between frames All the enabled transmitters are tri stated during these gaps 7 5 4 4 Byte Format LSB MSB for the Transmitter Some devices such as codecs require a MSB f...

Page 208: ... is latched by RX the latched values of SC 1 0 are latched by the respective SSISR IF 1 0 bits and can be read by software When programed as output flags the value of the SC 1 0 bits is taken from the value of the OF 1 0 bits The value of the OF 1 0 bits is latched when the contents of TX are transferred to the transmit shift register The value on SC 1 0 is stable from the time the first bit of th...

Page 209: ...19 shows the PRR bits Figure 7 18 Port Control Register PCR PCRC X FFFFBF PCRD X FFFFAF Figure 7 19 Port Direction Register PRR PRRC X FFFFBE PRRD X FFFFAE PC0 PC1 PC2 PC3 PC4 PC5 Reserved Bit Read As Zero Should Be Written With Zero For Future Compatibility 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 AA0688 STDn SRDn SCKn SCKn2 SCKn1 SCKn0 PCRC ESSI0 PCRD ESSI1 0 GPIO 1 ESSI 0 1...

Page 210: ...n the corresponding PD i bit reflects the value present on this signal If a port signal i is configured as a GPIO output then the value written into the corresponding PD i bit is reflected on the this signal Figure 7 20 shows the PDR bits Table 7 5 Port Control Register and Port Direction Register Bits PC i PDC i Port Signal i Function 1 X ESSI 0 0 GPIO input 0 1 GPIO output Note X The signal sett...

Page 211: ...7 46 DSP56309UM D MOTOROLA Enhanced Synchronous Serial Interface ESSI GPIO Signals and Registers Note Either a hardware RESET signal or a software RESET instruction clears all PDR bits ...

Page 212: ...MOTOROLA DSP56309UM D 8 1 SECTION 8 SERIAL COMMUNICATION INTERFACE SCI ...

Page 213: ...8 2 DSP56309UM D MOTOROLA Serial Communication Interface SCI 8 1 INTRODUCTION 8 3 8 2 SCI I O SIGNALS 8 3 8 3 SCI PROGRAMMING MODEL 8 4 8 4 OPERATING MODES 8 21 8 5 GPIO SIGNALS AND REGISTERS 8 27 ...

Page 214: ...ipherals The SCI consists of separate transmit and receive sections that can operate asynchronously with respect to each other A programmable baud rate generator provides the transmit and receive clocks An enable vector and an interrupt vector have been included so that the baud rate generator can function as a general purpose timer when it is not being used by the SCI or when the interrupt timing...

Page 215: ...al PE1 when the SCI TXD function is not being used 8 2 3 SCI Serial Clock SCLK This bidirectional signal provides an input or output clock from which the transmit and or receive baud rate is derived in asynchronous mode and from which data is transferred in synchronous mode SCLK can be programmed as a GPIO signal PE2 when the SCI SCLK function is not being used This signal can be programmed as PE2...

Page 216: ...ing on page 8 6 Figure 8 4 shows the formats of data words 7 6 5 4 3 2 1 0 WOMS RWU WAKE SBK SSFTD WDS2 WDS1 WDS0 15 14 13 12 11 10 9 8 SCKP STIR TMIE TIE RIE ILIE TE RE 23 22 21 20 19 18 17 16 REIE AA0854 Figure 8 1 SCI Control Register SCR 7 6 5 4 3 2 1 0 R8 FE PE OR IDLE RDRF TDRE TRNE 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 AA0855 Figure 8 2 SCI Status Register SSR 7 6 5 4 3 2 1 0 CD7 CD...

Page 217: ...ous 1 Start 8 Data 1 Odd Parity 1 Stop TX SSFTD 0 Start Bit D7 or Data Type Stop Bit Odd Parity Mode 6 11 bit Asynchronous Multidrop 1 Start 8 Data 1 Data Type 1 Stop TX SSFTD 0 Start Bit Stop Bit Data Type Note 1 Modes 1 3 and 7 are reserved 2 D0 LSB D7 MSB 3 Data is transmitted and received LSB first if SSFTD 0 or MSB first if SSFTD 1 D0 D1 D2 D3 D4 D5 D6 D7 0 1 0 D0 D1 D2 D3 D4 D5 D6 WDS2 WDS1 ...

Page 218: ...rt 8 Data 1 Odd Parity 1 Stop TX SSFTD 1 Start Bit D0 or Data Type Stop Bit Odd Parity Mode 6 11 bit Asynchronous Multidrop 1 Start 8 Data 1 Data Type 1 Stop TX SSFTD 1 Start Bit Stop Bit Data Type D7 D6 D5 D4 D3 D2 D1 D0 WDS2 WDS1 WDS0 0 0 0 Note 1 Modes 1 3 and 7 are reserved 2 D0 LSB D7 MSB 3 Data is transmitted and received LSB first if SSFTD 0 or MSB first if SSFTD 1 0 Data Byte Data Type 1 A...

Page 219: ...ster used for I O expansion and stream mode channel interfaces A gated transmit and receive clock compatible with the Intel 8051 serial interface mode 0 makes it possible for you to synchronize data When odd parity is selected the transmitter counts the number of 1s in the data word If the total is not an odd number the parity bit is set thus producing an odd number If the receiver counts an even ...

Page 220: ... bit Either a hardware RESET signal or a software RESET instruction clears SBK 8 3 1 4 SCR Wakeup Mode Select WAKE Bit 5 When WAKE is cleared the wakeup on idle line mode is selected In the wakeup on idle line mode the SCI receiver is reenabled by an idle string of at least ten or eleven depending on WDS mode consecutive 1s The transmitterÕs software must provide this idle string between consecuti...

Page 221: ...o ignore the remainder of the message and wait for the next message Either a hardware RESET signal or a software RESET instruction clears RWU RWU is ignored in synchronous mode 8 3 1 6 SCR Wired OR Mode Select WOMS Bit 7 When the WOMS bit is set the SCI TXD driver is programmed to function as an open drain output and can be wired together with other TXD signals in an appropriate bus configuration ...

Page 222: ...first byte of the second message is not transferred to STX prior to the finish of the preamble transmission the transmit data line marks idle until STX is finally written 8 3 1 9 SCR Idle Line Interrupt Enable ILIE Bit 10 When ILIE is set the SCI interrupt occurs when IDLE SCI status register bit 3 is set When ILIE is cleared the IDLE interrupt is disabled Either a hardware RESET signal or a softw...

Page 223: ...he SCI baud rate generator as a simple periodic interrupt generator if the SCI is not in use if external clocks are used for the SCI or if periodic interrupts are needed at the SCI baud rate The SCI internal clock is divided by 16 to match the 1 SCI baud rate for timer interrupt generation This timer does not require that any SCI signals be configured for SCI use to operate Either a hardware RESET...

Page 224: ...ing data into the STX or the STXA or when an idle preamble or break is transmitted This bit when set indicates that the transmitter is empty therefore the data written to STX or STXA is transmitted next That is there is no word in the transmit shift register presently being transmitted This procedure is useful when initiating the transfer of a message i e a string of characters TRNE is set by a ha...

Page 225: ... reset or STOP instruction 8 3 2 5 SSR Overrun Error Flag OR Bit 4 The OR flag bit is set when a byte is ready to be transferred from the receive shift register to the receive data register SRX that is already full RDRF 1 The receive shift register data is not transferred to the SRX The OR flag indicates that character s in the received data stream may have been lost The only valid data is located...

Page 226: ...gister SCCR The SCCR is a 24 bit read write register that controls the selection of the clock modes and baud rates for the transmit and receive sections of the SCI interface The control bits are described in the following paragraphs The SCCR is cleared by a hardware RESET signal The basic features of the clock generator as in Figure 8 5 on page 8 16 and Figure 8 6 on page 8 18 are these The SCI lo...

Page 227: ...al or a software RESET instruction clears CD11ÐCD0 8 3 3 2 SCCR Clock Out Divider COD Bit 12 The clock output divider is controlled by COD and SCI mode If SCI mode is synchronous the output divider is fixed at divide by 2 If SCI mode is asynchronous then one of the following conditions occurs If COD is cleared and SCLK is an output i e TCM and RCM are both cleared the SCI clock is divided by 16 be...

Page 228: ... 3 3 4 SCCR Receive Clock Mode Source RCM Bit 14 RCM selects whether an internal or external clock is used for the receiver If RCM is cleared the internal clock is used If RCM is set the external clock from the SCLK signal is used Either a hardware RESET signal or a software RESET instruction clears RCM Table 8 2 TCM and RCM Bit Configuration TCM RCM TX Clock RX Clock SCLK Signal Mode 0 0 Internal...

Page 229: ...ransmit as in Figure 8 7 There are two receive registersÑa receive data register SRX and a serial to parallel receive shift register There are also two transmit registersÑa transmit data register called either STX or STXA and a parallel to serial transmit shift register Figure 8 6 SCI Baud Rate Generator Fcore Divide By 2 12 bit Counter Prescaler Divide by 1 or 8 CD11ÐCD0 SCP Internal Clock Timer ...

Page 230: ... of SRX are placed in the middle byte of the bus and when SRXH is read the contents of SRX are placed in the high byte with the remaining bits read as 0s Mapping SRX as described allows three bytes to be efficiently packed into one 24 bit word by ORing three data bytes read from the three addresses Figure 8 7 SCI Programming Model Data Registers SRX SRX SRX RXD SCI Receive Data Shift Register Note...

Page 231: ...ack the bytes in a 24 bit word for transmission TDXA should be written in the 11 bit asynchronous multidrop mode when the data is an address and it is desired that the ninth bit the address bit be set When STXA is written the data from the low byte on the data bus is stored in it The address data bit is cleared in the 11 bit asynchronous multidrop mode when any of STXL STXM or STXH is written When...

Page 232: ... two cycles the bit does not reflect its current status See the DSP56300 Family Manual Appendix B Polling a Peripheral Device for Write for further details 8 4 OPERATING MODES The operating modes for the DSP56309 SCI are these 8 bit synchronous shift register mode 10 bit asynchronous 1 start 8 data 1 stop 11 bit asynchronous 1 start 8 data 1 even parity 1 stop 11 bit asynchronous 1 start 8 data 1 ...

Page 233: ...e SCI I O signals is not programmed as GPIO 3 Individual reset During program execution the PC2 PC1 and PC0 bits can be cleared individual reset which causes the SCI to stop serial activity and enter the reset state All SCI status bits are set to their reset state However the contents of the SCR are not affected allowing the DSP program to reset the SCI separately from the other internal periphera...

Page 234: ...Reset SW Reset IR Reset ST Reset REIE 16 0 0 Ñ Ñ SCKP 15 0 0 Ñ Ñ STIR 14 0 0 Ñ Ñ TMIE 13 0 0 Ñ Ñ TIE 12 0 0 Ñ Ñ RIE 11 0 0 Ñ Ñ ILIE 10 0 0 Ñ Ñ TE 9 0 0 Ñ Ñ SCR RE 8 0 0 Ñ Ñ WOMS 7 0 0 Ñ Ñ RWU 6 0 0 Ñ Ñ WAKE 5 0 0 Ñ Ñ SBK 4 0 0 Ñ Ñ SSFTD 3 0 0 Ñ Ñ WDS 2 0 2Ð0 0 0 Ñ Ñ R8 7 0 0 0 0 FE 6 0 0 0 0 PE 5 0 0 0 0 SSR OR 4 0 0 0 0 IDLE 3 0 0 0 0 RDRF 2 0 0 0 0 TDRE 1 1 1 1 1 ...

Page 235: ...3 0 23Ð0 Ñ Ñ Ñ Ñ SRSH SRS 8 0 8Ð0 Ñ Ñ Ñ Ñ STSH STS 8 0 8Ð0 Ñ Ñ Ñ Ð Note SRSHÑSCI Receive Shift Register STSH Ñ SCI Transmit Shift Register HWÑHardware reset is caused by asserting the external RESET signal SWÑSoftware reset is caused by executing the RESET instruction IRÑIndividual reset is caused by clearing PCRE bits 0Ð2 configured for GPIO STÑStop reset is caused by executing the STOP instructi...

Page 236: ...at would be in use during the operation no interrupt occurs 3 Enable the SCI by setting the PCR bits according to which signals will be in use during operation 4 If transmit interrupt is not used write data to the transmitter If transmitter interrupt enable is set an interrupt is issued and the interrupt handler should write data into the transmitter SCI transmit request is serviced by DMA channel...

Page 237: ...gister followed by a read of SRX A long interrupt service routine should be used to handle the error condition This interrupt is enabled by SCR bit 16 REIE 2 SCI receive data is caused by receive data register full Reading SRX clears the pending interrupt This error free interrupt can use a fast interrupt service routine for minimum overhead This interrupt is enabled by SCR bit 11 RIE 3 SCI transm...

Page 238: ...onding port signal is configured as a GPIO signal Bits in the Port E control register appear in Figure 8 8 Note A hardware RESET signal or a software RESET instruction clears all PCR bits 8 5 2 Port E Direction Register PRRE The read write 24 bit PRRE controls the direction of SCI GPIO signals When port signal i is configured as GPIO PDC i controls the port signal direction When PDC i is set the G...

Page 239: ...ignal i is configured as a GPIO input then the corresponding PD i bit reflects the value of this signal If a port signal i is configured as a GPIO output then the value of the corresponding PD i bit is reflected on this signal Bits of the Port E data register appear in Figure 8 10 Figure 8 9 Port E Direction Register PRRE Table 8 4 Port Control Register and Port Direction Register Bits PC i PDC i ...

Page 240: ...M D 8 29 Note A hardware RESET signal or a software RESET instruction clears all PDRE bits Figure 8 10 Port E Data Register PDRE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PD0 PD1 PD2 16 17 18 19 20 21 22 23 Reserved Bit Read as 0 Should be Written with 0 for Future Compatibility AA0697 ...

Page 241: ...8 30 DSP56309UM D MOTOROLA Serial Communication Interface SCI GPIO Signals and Registers ...

Page 242: ...MOTOROLA DSP56309UM D 9 1 SECTION 9 TRIPLE TIMER MODULE ...

Page 243: ...9 2 DSP56309UM D MOTOROLA Triple Timer Module 9 1 INTRODUCTION 9 3 9 2 TRIPLE TIMER MODULE ARCHITECTURE 9 3 9 3 TRIPLE TIMER MODULE PROGRAMMING MODEL 9 5 9 4 TIMER OPERATIONAL MODES 9 16 ...

Page 244: ...nal an external device after counting internal events Each timer can also be used to trigger DMA transfers after a specified number of events clocks has occurred Each timer connects to the external world through one bidirectional signal designated TIO0ÐTIO2 for Timers 0Ð2 respectively When the TIO signal is configured as input the timer functions as an external event counter or measures external p...

Page 245: ...nd status register TCSR a 24 bit read only timer count register TCR a 24 bit write only timer load register TLR a 24 bit read write timer compare register TCPR and logic for clock selection and interrupt DMA trigger generation The timer mode is controlled by the TC 3 0 bits of the timer control status register TCSR For a listing of the timer modes see Section 9ÑTimer Operational Modes For a descri...

Page 246: ...ques can be used to service the timers The timer programming model is shown in Figure 9 3 on page 9 6 9 3 TRIPLE TIMER MODULE PROGRAMMING MODEL The programming model for the triple timer module appears in Figure 9 3 on page 9 6 Figure 9 2 Timer Module Block Diagram GDB Control Status Register TCSR Counter Timer interrupt Timer Control CLK 2 TIO Compare Register TCPR 24 24 DMA request Logic Load Re...

Page 247: ... should be written with 0 for future compatibility 23 0 Timer Load Register TLR 23 22 21 20 19 18 17 16 23 0 Timer Compare Register TCPR PCE TRM TCF TOF TOIE TC2 23 0 Timer Count Register TCR TC3 TCSR0 FFFF8F TCSR1 FFFF8B TCSR2 FFFF87 TLR0 FFFF8E TLR1 FFFF8A TLR2 FFFF86 TCR0 FFFF8C TCR1 FFFF88 TCR2 FFFF84 TCPR0 FFFF8D TCPR1 FFFF89 TCPR2 FFFF85 23 0 Timer Prescaler Load Register TPLR TPLR FFFF83 23...

Page 248: ... bits contain the prescaler preload value This value is loaded into the prescaler counter when the counter value reaches 0 or the counter switches state from disabled to enabled If PL 20 0 N then the prescaler counts N 1 source clock cycles before generating a prescaler clock pulse Therefore the prescaler divide factor preload value 1 The PL 20 0 bits are cleared by a hardware RESET signal or a so...

Page 249: ...sable the prescaler counter by clearing the TE bit in the TCSR of each of three timers 9 3 2 3 TPLR Reserved Bit 23 This reserved bit is read as 0 and should be written with 0 for future compatibility 9 3 3 Timer Prescaler Count Register TPCR The TPCR is a 24 bit read only register that reflects the current value in the prescaler counter The register bits are shown in Figure 9 5 Table 9 1 Prescale...

Page 250: ...bit disables the timer The TE bit is cleared by a hardware RESET signal or a software RESET instruction Note When all three timers are disabled and the signals are not in GPIO mode all three TIO signals are tri stated To prevent undesired spikes on the TIO signals when switching from tri state into active state these signals should be tied to the high or low signal state by the use of pull up or p...

Page 251: ... 9 3 4 4 Timer Control TC 3 0 Bits 4 7 The four TC bits control the source of the timer clock the behavior of the TIO signal and timer mode Table 9 2 summarizes the TC bit functionality There is a detailed description of the timer operating modes in Section 9 4ÑTimer Operational Modes The TC bits are cleared by a hardware RESET signal or a software RESET instruction Note If the clock is external t...

Page 252: ... Input Internal 0 1 0 1 5 Input Period Measurement Input Internal 0 1 1 0 6 Capture Event Input Internal 0 1 1 1 7 Pulse Width Modulation PWM Output Internal 1 0 0 0 8 Reserved Ñ Ñ 1 0 0 1 9 Watchdog Pulse Output Internal 1 0 1 0 10 Watchdog Toggle Output Internal 1 0 1 1 11 Reserved Ñ Ñ 1 1 0 0 12 Reserved Ñ Ñ 1 1 0 1 13 Reserved Ñ Ñ 1 1 1 0 14 Reserved Ñ Ñ 1 1 1 1 15 Reserved Ñ Ñ Note 1 The GPIO...

Page 253: ...e TIO signal Ñ Ñ 2 Counter is incremented on the rising edge of the signal from the TIO signal Counter is incremented on the falling edge of the signal from the TIO signal TCRx output put on TIO signal directly TCRx output inverted and put on TIO signal 3 Counter is incremented on the rising edge of the signal from the TIO signal Counter is incremented on the falling edge of the signal from the TI...

Page 254: ...ceived If the TRM bit is set the counter is reloaded each time after it reaches the value contained by the TCR In PWM mode 7 the counter is reloaded each time counter overflow occurs In measurement 4Ð5 modes if the TRM and the TE bits are set the counter is preloaded with the TLR value on each appropriate edge of the input signal If the TRM bit is cleared the counter operates as a free running cou...

Page 255: ...alue of the DO bit is inverted when written to the TIO signal When the INV bit is cleared the value of the DO bit is written directly to the TIO signal When GPIO mode is disabled writing the DO bit has no effect The DO bit is cleared by a hardware RESET signal or a software RESET instruction 9 3 4 10 Prescaler Clock Enable PCE Bit 15 The PCE bit is used to select the prescaler clock as the timer s...

Page 256: ...SR Reserved Bits 3 10 14 16 19 22 23 These reserved bits are read as 0 and should be written with 0 for future compatibility 9 3 5 Timer Load Register TLR The TLR is a 24 bit write only register In all modes the counter is preloaded with the TLR value after the TE bit in the TCSR is set and a first event occurs In timer modes if the timer reload mode TRM bit in the TCSR is set the counter is reloa...

Page 257: ...the TCR is loaded with the current value of the counter on the appropriate edge of the input signal and its value can be read to determine the width period or delay of the leading edge of the input signal When the timer is in measurement modes the TIO signal is used for the input signal 9 4 TIMER OPERATIONAL MODES Each timer has these operational modes to meet a variety of system requirements Time...

Page 258: ...wing timing modes are provided Timer GPIO Timer pulse Timer toggle Event counter 9 4 1 1 Timer GPIO Mode 0 In this mode the timer generates an internal interrupt when a counter value is reached if the timer compare interrupt is enabled Set the TE bit to clear the counter and enable the timer Load the value the timer is to count into the TCPR The counter is loaded with the TLR value when the first ...

Page 259: ...can be taken from either the DSP56309 clock divided by two CLK 2 or from the prescaler clock output Each subsequent clock signal increments the counter When the counter matches the TCPR value the TCF bit in TCSR is set and a compare interrupt is generated if the TCIE bit is set The polarity of the TIO signal is inverted for one timer clock period If the TRM bit is set the counter is loaded with th...

Page 260: ...e TIO output signal is inverted The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set If the TRM bit is set the counter is loaded with the value of the TLR when the next timer clock is received and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the TE bit is cleared disab...

Page 261: ...ransitions or high to low 1 to 0 transitions increment the counter If the INV bit is set high to low transitions increment the counter If the INV bit is cleared low to high transitions increment the counter When the counter matches the value contained in the TCPR the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set If the TRM bit is set the counter is loaded w...

Page 262: ... by two CLK 2 or from the prescaler clock input Each subsequent clock signal increments the counter If the INV bit is set the timer starts on the first high to low 1 to 0 signal transition on the TIO signal If the INV bit is cleared the timer starts on the first low to high 0 to 1 transition on the TIO signal When the first transition opposite in polarity to the INV bit setting occurs on the TIO s...

Page 263: ...eceived from either the DSP56309 clock divided by two CLK 2 or the prescaler clock output Each subsequent clock signal increments the counter On the next signal transition of the same polarity that occurs on TIO the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set The contents of the counter are loaded into the TCR The TCR then contains the value of the time t...

Page 264: ...bit in the TCSR is set and if the TCIE bit is set a compare interrupt is generated the counter halts and the contents of the counter are loaded into the TCR The value of the TCR represents the delay between the setting of the TE bit and the detection of the first clock edge signal on the TIO signal The value of the INV bit determines whether a high to low 1 to 0 or low to high 0 to 1 transition of...

Page 265: ...ow interrupt is generated if the TOIE bit is set If the TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the timer is disabled by clearing the TE bit TIO signal polarity is determined by the value of the INV bit When the counte...

Page 266: ...imer clock Set the TE bit to clear the counter and enable the timer The value to which the timer is to count is loaded into the TCPR The counter is loaded with the TLR value on the first timer clock received from either the DSP56309 internal clock divided by two CLK 2 or the prescaler clock output Each subsequent timer clock increments the counter When the counter matches the value of the TCPR the...

Page 267: ...h the timer is to count is loaded into the TPCR The counter is loaded with the TLR value on the first timer clock received from either the DSP56309 internal clock divided by two CLK 2 or the prescaler clock output Each subsequent timer clock increments the counter The TIO signal is set to the value of the INV bit When the counter equals the value in the TCPR the TCF bit in the TCSR is set and a co...

Page 268: ...rvices the interrupt 9 4 6 2 Timer Behavior during Stop During the execution of the STOP instruction the timer clocks are disabled timer activity is stopped and the TIO signals are disconnected Any external changes that happen to the TIO signals are ignored when the DSP56309 is in the stop state To insure correct operation the timers should be disabled before the DSP56309 is placed into the stop s...

Page 269: ...9 28 DSP56309UM D MOTOROLA Triple Timer Module Timer Operational Modes ...

Page 270: ...MOTOROLA DSP56309UM D 10 1 SECTION 10 ON CHIP EMULATION MODULE ...

Page 271: ...ORY BREAKPOINT LOGIC 10 9 10 6 ONCE TRACE LOGIC 10 15 10 7 METHODS OF ENTERING DEBUG MODE 10 16 10 8 PIPELINE INFORMATION AND OGDB REGISTER 10 18 10 9 DEBUGGING RESOURCES 10 20 10 10 SERIAL PROTOCOL DESCRIPTION 10 22 10 11 TARGET SITE DEBUG SYSTEM REQUIREMENTS 10 23 10 12 ONCE MODULE EXAMPLES 10 23 10 13 JTAG PORT ONCE MODULE INTERACTION 10 29 ...

Page 272: ... even when the chip is operating in normal mode See Section 11ÑJTAG Port for a description of the JTAG functionality and its relation to the OnCE module Figure 10 1 shows the block diagram of the OnCE module 10 2 OnCE MODULE SIGNALS The OnCE module controller functionality is accessed through the JTAG port There are no dedicated OnCE module signals for the clock data in or data out The JTAG signal...

Page 273: ...e deasserted after the OnCE port responds with an acknowledge and before sending the first OnCE command The assertion of this signal by the DSP56300 core indicates that the DSP has entered debug mode and is waiting for commands to be entered from the TDI line The DE signal also facilitates multiple processor connections as shown in Figure 10 2 In this way the user can stop all the devices in the s...

Page 274: ...ad write operation See Table 10 4 for the OnCE register select encoding 10 4 1 2 Exit Command EX Bit 5 If the EX bit is set leave debug mode and resume normal operation The EXIT command is executed only if the GO command is issued and the operation is write to OPDBR or Figure 10 3 OnCE Controller Block Diagram Figure 10 4 OnCE Command Register OnCE Command Register TDI TCK Status and Control Regis...

Page 275: ...PDBR or read write to ÒNo Register SelectedÓ Otherwise the GO bit is ignored Table 10 2 shows the definition of the GO bit 10 4 1 4 Read Write Command R W Bit 7 The R W bit as shown in Table 10 3 specifies the direction of data transfer Table 10 4 shows how to encode OnCE register selections Table 10 1 EX Bit Definition EX Action 0 Remain in Debug mode 1 Leave Debug mode Table 10 2 GO Bit Definiti...

Page 276: ...gister OGDBR 01010 PDB Register OPDBR 01011 PIL Register OPILR 01100 PDB GO TO Register for GO TO command 01101 Trace Counter OTC 01110 Reserved Address 01111 PAB Register for Fetch OPABFR 10000 PAB Register for Decode OPABDR 10001 PAB Register for Execute OPABEX 10010 Trace Buffer and Increment Pointer 10011 Reserved Address 101xx Reserved Address 11xx0 Reserved Address 11x0x Reserved Address 110...

Page 277: ...R is shown in Figure 10 5 10 4 3 1 Trace Mode Enable TME Bit 0 The TME control bit when set enables trace mode 10 4 3 2 Interrupt Mode Enable IME Bit 1 The IME control bit when set causes the chip to execute a vectored interrupt to the address VBA 06 instead of entering debug mode 10 4 3 3 Software Debug Occurrence SWO Bit 2 The SWO bit is a read only status bit that is set when debug mode is ente...

Page 278: ...uction core waiting for the bus STOP or WAIT instruction etc These bits are also reflected in the JTAG instruction shift register which allows the polling of the core status information at the JTAG level This is useful when the DSP56300 core executes the STOP instruction and therefore there are no clocks to allow the reading of OSCR See Table 10 5 for the definition of the OS0ÐOS1 bits 10 4 3 8 Re...

Page 279: ...gram at a specific point to examine change registers or memory Using address comparators to set breakpoints enables the user to set breakpoints in RAM or ROM and while in any operating mode Memory accesses are monitored according to the contents of the OBCR as specified in Section 10 5 6ÑOnCE Breakpoint Control Register OBCR Figure 10 6 OnCE Memory Breakpoint Logic 0 Memory Address Latch PAB XAB Y...

Page 280: ...JTAG port Before enabling breakpoints OMLR0 must be loaded by the external command controller 10 5 3 OnCE Memory Address Comparator 0 OMAC0 The OMAC0 compares the current memory address stored in OMAL0 with the OMLR0 contents 10 5 4 OnCE Memory Limit Register 1 OMLR1 The OMLR1 is a 16 bit register that stores the memory breakpoint limit OMLR1 can be read or written through the JTAG port Before ena...

Page 281: ...able 10 6 for the definition of the MBS0ÐMBS1 bits 10 5 6 2 Breakpoint 0 Read Write Select RW00ÐRW01 Bits 2Ð3 The RW00ÐRW01 bits define the memory breakpoint 0 to occur when a memory address access is performed for read write or both See Table 10 7 for the definition of the RW00ÐRW01 bits Figure 10 7 OnCE Breakpoint Control Register OBCR Table 10 6 Memory Breakpoint 0 and 1 Select Table MBS1 MBS0 ...

Page 282: ...y address access is performed for read write or both See Table 10 9 for the definition of the RW10ÐRW11 bits Table 10 7 Breakpoint 0 Read Write Select Table RW01 RW00 Description 0 0 Breakpoint disabled 0 1 Breakpoint on write access 1 0 Breakpoint on read access 1 1 Breakpoint on read or write access Table 10 8 Breakpoint 0 Condition Select Table CC01 CC00 Description 0 0 Breakpoint on not equal ...

Page 283: ...ne that a memory access event should occur before a memory breakpoint is declared The memory access event is specified by the OBCR and by the memory limit registers On each occurrence of the memory access event the breakpoint counter is decremented When the counter reaches 0 and a new occurrence takes place the chip enters debug mode The OMBC can be read or written through the JTAG port Every time...

Page 284: ...l port The OnCE trace logic block diagram is shown in Figure 10 8 Trace mode has a counter associated with it so that more than one instruction can be executed before returning back to debug mode The objective of the counter is to allow the user to take multiple instruction steps real time before entering debug mode This feature helps the software developer debug sections of code that do not have ...

Page 285: ...hardware RESET signal 10 7 METHODS OF ENTERING DEBUG MODE Entering debug mode is acknowledged by the chip by setting the core status bits OS1 and OS0 and asserting the DE line This informs the external command controller that the chip has entered debug mode and is waiting for commands The DSP56300 core can disable the OnCE module if the ROM Security option is implemented If the ROM security is imp...

Page 286: ...he external command controller that debug mode has been entered 10 7 4 External Debug Request During Stop Executing the JTAG instruction DEBUG_REQUEST or asserting DE while the chip is in the stop state i e has executed a STOP instruction causes the chip to exit the stop state and enter debug mode After receiving the acknowledge the external command controller must negate DE before sending the fir...

Page 287: ...p to enter debug mode 10 7 8 Enabling Memory Breakpoints When the memory breakpoint mechanism is enabled with a breakpoint counter value of 0 the chip enters debug mode after completing the execution of the instruction that caused the memory breakpoint to occur In case of breakpoints on executed program memory fetches the breakpoint is acknowledged immediately after the execution of the fetched in...

Page 288: ...OnCE PIL Register OPILR The OPILR is a 24 bit latch that stores the value of the instruction latch before debug mode is entered OPILR can only be read through the JTAG port Note Since the instruction latch is affected by the operations performed during debug mode it must be restored by the external command controller when returning to normal mode Since there is no direct write access to the instru...

Page 289: ... registers that give pipeline information when debug mode is entered and a trace buffer that stores the address of the last instruction that was executed as well as the addresses of the last 12 change of flow instructions 10 9 1 OnCE PAB Register for Fetch OPABFR The OPABFR is a 16 bit register that stores the address of the last instruction whose fetch was started before debug mode was entered Th...

Page 290: ... instructions The first trace buffer read obtains the oldest address and the following trace buffer reads get the other addresses from the oldest to the newest in order of execution Notes 1 To insure trace buffer coherence a complete set of 12 reads of the Trace buffer must be performed This is necessary due to the fact that each read increments the trace buffer pointer thus pointing to the next l...

Page 291: ...00 core chip the following protocol is adopted Before starting any debugging activity the external command controller has to wait for an acknowledge Figure 10 10 OnCE Trace Buffer Fetch Address OPABFR PAB Decode Address OPABDR Circular Buffer Pointer Trace Buffer Shift Register TDO TCK Trace Buffer Register 0 Trace Buffer Register 1 Trace Buffer Register 2 Trace Buffer Register 11 Execute Address ...

Page 292: ... are shown in Figure 10 4 on page 10 5 10 11 TARGET SITE DEBUG SYSTEM REQUIREMENTS A typical debug environment consists of a target system where the DSP56300 core based device resides in the user defined hardware The JTAG port interfaces to the external command controller over a 8 wire link consisting of the five JTAG port wires one OnCE module wire a ground and a reset wire The reset wire is opti...

Page 293: ...troller can poll the JTAG instruction shift register for the status bits OS 1 0 When the chip is in Debug mode these bits are set to the value 11 Note In the following paragraphs the ACK notation denotes the operation performed by the command controller to check whether debug mode has been entered either by sensing DE or by polling JTAG instruction shift register 10 12 2 Polling the JTAG Instructi...

Page 294: ...s no need to verify acknowledge between steps 1 and 2 as well as 3 and 4 because completion is guaranteed by design 10 12 4 Reading the Trace Buffer An optional step during debugging activity is reading the information associated with the trace buffer in order to enable an external program to reconstruct the full trace of the executed program In the following description of the read trace buffer p...

Page 295: ... DSP56300 must be in debug mode and all actions described in Section 10 12 3ÑSaving Pipeline Information have been executed The sequence of actions is as follows 1 Select shift DR Shift in the ÒWrite PDB with GO no EXÓ Pass through update DR 2 Select shift DR Shift in the 24 bit opcode ÒMOVE reg X OGDBÓ Pass through update DR to actually write OPDBR and thus begin executing the MOVE instruction 3 ...

Page 296: ...OVE xxxx R0Ó the xxxx field Pass through update DR to actually write OPDBR and execute the instruction R0 is loaded with the base address of the memory block to be read 10 Wait for DSP to reenter debug mode Wait for DE or poll core status 11 Select shift DR Shift in the ÒWrite PDB with GO no EXÓ Pass through update DR 12 Select shift DR Shift in the 24 bit opcode ÒMOVE X R0 X OGDBÓ Pass through up...

Page 297: ...hip from debug mode and the normal flow of execution is continued 10 12 8 Returning from Debug to Normal Mode New Program In this case you have finished examining the current state of the machine changed some of the registers and wish to start the execution of a new program the GOTO command Therefore you must force a Òchange of flowÓ to the starting address of the new program xxxx The sequence of ...

Page 298: ...able 10 12 The sequence to enable the OnCE module appears in Table 10 13 After executing the JTAG instructions DEBUG_REQUEST and ENABLE_ONCE and after the core status was polled to verify that the chip is in debug mode the pipeline saving procedure must take place The TMS sequencing for this procedure is depicted in Table 10 12 Table 10 12 TMS Sequencing for DEBUG_REQUEST Step TMS JTAG Port OnCE M...

Page 299: ...e n 0 Run Test Idle Idle This step is repeated enabling an external command controller to poll the status n 0 Run Test Idle Idle Table 10 13 TMS Sequencing for ENABLE_ONCE Step TMS JTAG Port OnCE Module Note a 1 Test Logic Reset Idle Ñ b 0 Run Test Idle Idle Ñ c 1 Select DR Scan Idle Ñ d 1 Select IR Scan Idle Ñ e 0 Capture IR Idle The core status bits are captured f 0 Shift IR Idle The four bits o...

Page 300: ...ct DR Scan Idle Ñ c 0 Capture DR Idle Ñ d 0 Shift DR Idle The eight bits of the OnCE command ÒRead PILÓ 10001011 are shifted in d 0 Shift DR Idle e 1 Exit1 DR Idle Ñ f 1 Update DR Execute ÒRead PILÓ The PIL value is loaded in the shifter g 1 Select DR Scan Idle Ñ h 0 Capture DR Idle Ñ i 0 Shift DR Idle The 24 bits of the PIL are shifted out 24 steps i 0 Shift DR Idle j 1 Exit1 DR Idle Ñ k 1 Update...

Page 301: ...fted in n 0 Shift DR Idle o 1 Exit1 DR Idle Ñ p 1 Update DR Execute ÒRead PDBÓ PDB value is loaded in shifter q 1 Select DR Scan Idle Ñ r 0 Capture DR Idle Ñ s 0 Shift DR Idle The 24 bits of the PDB are shifted out 24 steps s 0 Shift DR Idle t 1 Exit1 DR Idle Ñ u 1 Update DR Idle Ñ v 0 Run Test Idle Idle This step can be repeated enabling an external command controller to analyze the information v...

Page 302: ...MOTOROLA DSP56309UM D 11 1 SECTION 11 JTAG PORT ...

Page 303: ...11 2 DSP56309UM D MOTOROLA JTAG Port 11 1 INTRODUCTION 11 3 11 2 JTAG SIGNALS 11 4 11 3 TAP CONTROLLER 11 6 11 4 DSP56300 RESTRICTIONS 11 12 11 5 DSP56309 BOUNDARY SCAN REGISTER 11 13 ...

Page 304: ... effectively reducing the BSR to a single cell BYPASS Samples the DSP56300 core based device system signals during operation and transparently shifts out the result in the BSR Preloads values to output signals prior to invoking the EXTEST instruction SAMPLE PRELOAD Disables the output drive to signals during circuit board testing HI Z Provides a means of accessing the OnCE controller and circuits ...

Page 305: ...document the JTAG port requires a minimum of four signals to support TDI TDO TCK and TMS signals The DSP56300 family also provides Figure 11 1 TAP Block Diagram Boundary Scan Register Bypass MUX 4 Bit Instruction Register TDO TAP Ctrl TDI TMS TCK 0 2 3 1 OnCE Logic ID Register TRST Decoder MUX AA0113 ...

Page 306: ...e The TMS is sampled on the rising edge of TCK and it has an internal pull up resistor 11 2 3 Test Data Input TDI Serial test instruction and data are received through the Test Data Input TDI signal TDI is sampled on the rising edge of TCK and it has an internal pull up resistor 11 2 4 Test Data Output TDO The TDO signal is the serial output for test instructions and data TDO is tri stateable and ...

Page 307: ...nsitions from one state to another occur on the rising edge of TCK The value shown adjacent to each state transition represents the value of the TMS signal sampled on the rising edge of TCK signal For a description of the TAP controller states refer to the IEEE 1149 1 document Figure 11 2 TAP Controller State Machine Select DR Scan Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Test Logic Reset Ru...

Page 308: ...fined by IEEE 1149 1 The HI Z public instruction provides the capability for disabling all device output drivers The ENABLE_ONCE public instruction enables the JTAG port to communicate with the OnCE circuitry The DEBUG_REQUEST public instruction enables the JTAG port to force the DSP56300 core into debug mode The DSP56300 core includes a 4 bit instruction register without parity consisting of a sh...

Page 309: ...dule for a description of the status bits 11 3 2 1 EXTEST B 3 0 0000 The external test EXTEST instruction selects the BSR EXTEST also asserts internal reset for the DSP56300 core system logic to force a predictable internal state while performing external boundary scan operations By using the TAP the BSR is capable of the following Scanning user defined values into the output buffers Capturing val...

Page 310: ...n is to initialize the BSR output cells prior to selection of EXTEST This initialization insures that known data appears on the outputs when entering the EXTEST instruction 11 3 2 3 IDCODE B 3 0 0010 The IDCODE instruction selects the ID register This instruction is provided as a public instruction to allow the manufacturer part number and version of a component to be determined through the TAP Fi...

Page 311: ...I and TDO while allowing signals driven from the component signals to be determined from the BSR During testing of ICs on PCB it may be necessary to place static guarding values on signals that control operation of logic not involved in the test The EXTEST instruction could be used for this purpose but because it selects the BSR the required guarding signals would be loaded as part of the complete...

Page 312: ... Due to the fact that in the Capture IR state of the TAP the OnCE status bits are captured in the Instruction shift register the external JTAG controller must continue to shift in the DEBUG_REQUEST instruction while polling the status bits that are shifted out until debug mode is entered acknowledged by the combination 11 on OS1ÐOS0 After the acknowledgment of debug mode is received the external J...

Page 313: ...controller into this state After power up is concluded TMS must be sampled as a logical 1 for five consecutive TCK rising edges If TMS either remains unconnected or is connected to VCC then the TAP controller cannot leave the Test Logic Reset state regardless of the state of TCK The DSP56300 core features a low power stop mode which is invoked using the STOP instruction The interaction of the JTAG...

Page 314: ...C_1 MODD Input Data 4 BC_6 D23 Input Output Data 5 BC_6 D22 Input Output Data 6 BC_6 D21 Input Output Data 7 BC_6 D20 Input Output Data 8 BC_6 D19 Input Output Data 9 BC_6 D18 Input Output Data 10 BC_6 D17 Input Output Data 11 BC_6 D16 Input Output Data 12 BC_6 D15 Input Output Data 13 BC_1 D 23 12 Ñ Control 14 BC_6 D14 Input Output Data 15 BC_6 D13 Input Output Data 16 BC_6 D12 Input Output Data ...

Page 315: ...C_2 A15 Output 2 Data 31 BC_2 A14 Output 2 Data 32 BC_2 A13 Output 2 Data 33 BC_2 A12 Output 2 Data 34 BC_2 A11 Output 2 Data 35 BC_2 A10 Output 2 Data 36 BC_2 A9 Output 2 Data 37 BC_2 A8 Output 2 Data 38 BC_2 A7 Output 2 Data 39 BC_2 A6 Output 2 Data 40 BC_2 A5 Output 2 Data 41 BC_2 A4 Output 2 Data 42 BC_2 A3 Output 2 Data 43 BC_2 A2 Output 2 Data 44 BC_2 A1 Output 2 Data 45 BC_2 A0 Output 2 Dat...

Page 316: ...C_1 HAD1 Ñ Control 56 BC_6 HAD1 Input Output Data 57 BC_1 HAD2 Ñ Control 58 BC_6 HAD2 Input Output Data 59 BC_1 HAD3 Ñ Control 60 BC_6 HAD3 Input Output Data 61 BC_1 HAD4 Ñ Control 62 BC_6 HAD4 Input Output Data 63 BC_1 HAD5 Ñ Control 64 BC_6 HAD5 Input Output Data 65 BC_1 HAD6 Ñ Control 66 BC_6 HAD6 Input Output Data 67 BC_1 HAD7 Ñ Control 68 BC_6 HAD7 Input Output Data 69 BC_1 HAS A0 Ñ Control T...

Page 317: ...ata 79 BC_1 TIO1 Ñ Control 80 BC_6 TIO1 Input Output Data 81 BC_1 TIO2 Ñ Control 82 BC_6 TIO2 Input Output Data 83 BC_1 HREQ TRQ Ñ Control 84 BC_6 HREQ TRQ Input Output Data 85 BC_1 HACK RRQ Ñ Control 86 BC_6 HACK RRQ Input Output Data 87 BC_1 HRW RD Ñ Control 88 BC_6 HRW RD Input Output Data 89 BC_1 HDS WR Ñ Control 90 BC_6 HDS WR Input Output Data 91 BC_1 SCK0 Ñ Control 92 BC_6 SCK0 Input Output...

Page 318: ... Data 103 BC_1 SC10 Ñ Control 104 BC_6 SC10 Input Output Data 105 BC_1 STD0 Ñ Control 106 BC_6 STD0 Input Output Data 107 BC_1 SRD0 Ñ Control 108 BC_6 SRD0 Input Output Data 109 BC_1 PINIT Ñ Control 110 BC_6 PINIT Input Output Data 111 BC_1 DE Ñ Control 112 BC_6 DE Input Output Data 113 BC_1 SC01 Ñ Control 114 BC_6 SC01 Input Output Data 115 BC_1 SC02 Ñ Control 116 BC_6 SC02 Input Output Data 117 ...

Page 319: ... 118 BC_6 STD1 Input Output Data 119 BC_1 SRD1 Ñ Control 120 BC_6 SRD1 Input Output Data 121 BC_1 SC11 Ñ Control 122 BC_6 SC11 Input Output Data 123 BC_1 SC12 Ñ Control Table 11 2 DSP56309 BSR Bit Definitions Continued Bit Cell Type Signal Name Signal Type BSR Cell Type ...

Page 320: ... memory of SRAM type is used The accesses will be performed using 31 wait states with no address attributes selected default area BOOTSTRAP CODE FOR DSP56309 C Copyright 1998 Motorola Inc Revised March 1998 Bootstrap through the Host Interface External EPROM or SCI This is the Bootstrap program contained in the DSP56309 192 word Boot ROM This program can load any program RAM segment from an extern...

Page 321: ...nd then 3 bytes for each program word to be loaded The number of words the starting address and the program words are read least significant byte first followed by the mid and then by the most significant byte The program words will be condensed into 24 bit words and stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execut...

Page 322: ...rogram words and then a 24 bit word for each program word to be loaded The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started The Host Interface bootstrap load program may be stopped by setting the Host Flag 0 HF0 This will start execution of...

Page 323: ...for each program word to be loaded The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started The Host Interface bootstrap load program may be stopped by setting the Host Flag 0 HF0 This will start execution of the loaded program from the specifi...

Page 324: ...omr OMR0XXX If MD MC MB MA 0xxx go to OMR0XXX jclr 2 omr EPRSCILD If MD MC MB MA 10xx load from EPROM SCI jclr 1 omr OMR1IS0 IF MD MC MB MA 110x look for ISA HC11 jclr 0 omr I8051HOSTLD If MD MC MB MA 1110 load from 8051 Host If MD MC MB MA 1111 load from MC68302 Host This is the routine which loads a program through the HI08 host port The program is downloaded from the host MCU with the following...

Page 325: ... when enabled spare 0 This bit should be set to 0 for future compatability HEN 0 When the HPCR register is modified HEN should be cleared HAEN 1 Host acknowledge is enabled HREN 1 Host requests are enabled HCSEN 1 Host chip select input enabled HA9EN 0 address 9 enable bit has no meaning in non multiplexed bus HA8EN 0 address 8 enable bit has no meaning in non multiplexed bus HGEN 0 Host GPIO pins...

Page 326: ...hen enabled spare 0 This bit should be set to 0 for future compatability HEN 0 When the HPCR register is modified HEN should be cleared HAEN 0 Host acknowledge is disabled HREN 1 Host requests are enabled HCSEN 1 Host chip select input enabled HA9EN 0 address 9 enable bit has no meaning in non multiplexed bus HA8EN 0 address 8 enable bit has no meaning in non multiplexed bus HGEN 0 Host GPIO pins ...

Page 327: ...ading enddo Must terminate the do loop bra HI08LOOP HI08NW movep x M_HRX p r0 Move the new word into its destination location in the program RAM nop pipeline delay HI08LOOP bra FINISH EPRSCILD jclr 1 omr EPROMLD If MD MC MB MA 1001 go load from EPROM jset 0 omr SCILD If MD MC MB MA 1011 reserved default to SCI This is the routine that loads from the SCI MD MC MB MA 1010 external SCI clock SCILD mo...

Page 328: ...OP9 read number of words and starting address movem p r2 a2 Get the 8 LSB from ext P mem asr 8 a a Shift 8 bit data into A1 _LOOP9 move a1 r0 starting address for load move a1 r1 save it in r1 a0 holds the number of words do a0 _LOOP10 read program words do 3 _LOOP11 Each instruction has 3 bytes movem p r2 a2 Get the 8 LSB from ext P mem asr 8 a a Shift 8 bit data into A1 _LOOP11 Go get another by...

Page 329: ...While all tests pass the SCK0 pin will continue to toggle When the test fails the DSP enters DEBUG and stops execution get PATTERN pointer clr b PATTERNS r6 b is the error accumulator move NUM_PATTERNS 1 m6 program runs forever in cyclic form configure SCK0 as gpio output PRRC register is cleared at reset movep b x M_PDRC clear GPIO data register bset SCK0 x M_PRRC Define SCK0 as output GPIO pin S...

Page 330: ...e length_pram n2 length of pram rep n2 move y0 p r2 write pram check memory contents if EQUALDATA x y ram symmetrical check dram clr a start_dram r0 restore pointer clear a do n0 _loopd move x r0 a1 a0 a2 0 eor x1 a add a b accumulate error in b move y r0 a1 a0 a2 0 eor x0 a add a b accumulate error in b _loopd else x y ram not symmetrical check xram clr a start_xram r0 restore pointer clear a do ...

Page 331: ... otherwise beq label1 bclr SCK0 x M_PDRC clear sck0 if error enddo terminate the loop normally bra burn1 and stop execution label1 if no error bchg SCK0 x M_PDRC toggle pin and keep on looping burn1 wait enter wait after test completion ORG PL PL PATTERNS dsm 4 align for correct modulo addressing ORG PL PATTERNS PL PATTERNS Each value is written to all memories dc 555555 dc AAAAAA dc 333333 dc F0F...

Page 332: ...DIX B EQUATES EQUATES for 56302 I O registers and ports Last update June 11 1995 page 132 55 0 0 0 opt mex ioequ ident 1 0 EQUATES for DSP56309 I O registers and ports Last update March 1998 page 132 55 0 0 0 opt mex ioequ ident 1 0 ...

Page 333: ... HI08 EQUATES B 3 B 3 SCI EQUATES B 4 B 4 ESSI EQUATES B 5 B 5 EXCEPTION PROCESSING EQUATES B 7 B 6 TIMER MODULE EQUATES B 9 B 7 DIRECT MEMORY ACCESS DMA EQUATES B 10 B 8 PHASE LOCKED LOOP PLL EQUATES B 12 B 9 BUS INTERFACE UNIT BIU EQUATES B 13 B 10 INTERRUPT EQUATES B 15 ...

Page 334: ...ister M_PDRE EQU FFFF9D Port E Data Register M_OGDB EQU FFFFFC OnCE GDB Register B 2 HOST INTERFACE HI08 EQUATES Host Interface HI08 Equates Register Addresses M_HCR EQU FFFFC2 Host Control Register M_HSR EQU FFFFC3 Host Status Register M_HPCR EQU FFFFC4 Host Polarity Control Register M_HBAR EQU FFFFC5 Host Base Address Register M_HRX EQU FFFFC6 Host Receive Register M_HTX EQU FFFFC7 Host Transmit...

Page 335: ...y M_HAP EQU F Host Acknowledge Polarity B 3 SCI EQUATES Serial Communications Interface SCI Equates Register Addresses M_STXH EQU FFFF97 SCI Transmit Data Register high M_STXM EQU FFFF96 SCI Transmit Data Register middle M_STXL EQU FFFF95 SCI Transmit Data Register low M_SRXH EQU FFFF9A SCI Receive Data Register high M_SRXM EQU FFFF99 SCI Receive Data Register middle M_SRXL EQU FFFF98 SCI Receive ...

Page 336: ...PE EQU 5 Parity Error M_FE EQU 6 Framing Error Flag M_R8 EQU 7 Received Bit 8 R8 Address SCI Clock Control Register M_CD EQU FFF Clock Divider Mask CD0 CD11 M_COD EQU 12 Clock Out Divider M_SCP EQU 13 Clock Prescaler M_RCM EQU 14 Receive Clock Mode Source Bit M_TCM EQU 15 Transmit Clock Source Bit B 4 ESSI EQUATES Enhanced Synchronous Serial Interface ESSI Equates Register Addresses Of SSI0 M_TX00...

Page 337: ...Divider Control Mask DC0 DC7 M_ALC EQU 18 Alignment Control ALC M_WL EQU 380000 Word Length Control Mask WL0 WL7 M_SSC1 EQU 22 Select SC1 as TR 0 drive enable SSC1 SSI Control Register B Bit Flags M_OF EQU 3 Serial Output Flag Mask M_OF0 EQU 0 Serial Output Flag 0 M_OF1 EQU 1 Serial Output Flag 1 M_SCD EQU 1C Serial Control Direction Mask M_SCD0 EQU 2 Serial Control 0 Direction M_SCD1 EQU 3 Serial...

Page 338: ... Register Full SSI Transmit Slot Mask Register A M_SSTSA EQU FFFF SSI Transmit Slot Bits Mask A TS0 TS15 SSI Transmit Slot Mask Register B M_SSTSB EQU FFFF SSI Transmit Slot Bits Mask B TS16 TS31 SSI Receive Slot Mask Register A M_SSRSA EQU FFFF SSI Receive Slot Bits Mask A RS0 RS15 SSI Receive Slot Mask Register B M_SSRSB EQU FFFF SSI Receive Slot Bits Mask B RS16 RS31 B 5 EXCEPTION PROCESSING EQ...

Page 339: ...Interrupt Priority Level Mask M_D3L0 EQU 18 DMA3 Interrupt Priority Level low M_D3L1 EQU 19 DMA3 Interrupt Priority Level high M_D4L EQU 300000 DMA4 Interrupt priority Level Mask M_D4L0 EQU 20 DMA4 Interrupt Priority Level low M_D4L1 EQU 21 DMA4 Interrupt Priority Level high M_D5L EQU C00000 DMA5 Interrupt priority Level Mask M_D5L0 EQU 22 DMA5 Interrupt Priority Level low M_D5L1 EQU 23 DMA5 Inter...

Page 340: ...r M_TLR2 EQU FFFF86 TIMER2 Load Register M_TCPR2 EQU FFFF85 TIMER2 Compare Register M_TCR2 EQU FFFF84 TIMER2 Count Register M_TPLR EQU FFFF83 TIMER Prescaler Load Register M_TPCR EQU FFFF82 TIMER Prescaler Count Register Timer Control Status Register Bit Flags M_TE EQU 0 Timer Enable M_TOIE EQU 1 Timer Overflow Interrupt Enable M_TCIE EQU 2 Timer Compare Interrupt Enable M_TC EQU F0 Timer Control ...

Page 341: ...FFFEE DMA0 Destination Address Register M_DCO0 EQU FFFFED DMA0 Counter M_DCR0 EQU FFFFEC DMA0 Control Register Register Addresses Of DMA1 M_DSR1 EQU FFFFEB DMA1 Source Address Register M_DDR1 EQU FFFFEA DMA1 Destination Address Register M_DCO1 EQU FFFFE9 DMA1 Counter M_DCR1 EQU FFFFE8 DMA1 Control Register Register Addresses Of DMA2 M_DSR2 EQU FFFFE7 DMA2 Source Address Register M_DDR2 EQU FFFFE6 ...

Page 342: ...DS0 EQU 2 DMA Destination Memory Space 0 M_DDS1 EQU 3 DMA Destination Memory Space 1 M_DAM EQU 3f0 DMA Address Mode Mask DAM5 DAM0 M_DAM0 EQU 4 DMA Address Mode 0 M_DAM1 EQU 5 DMA Address Mode 1 M_DAM2 EQU 6 DMA Address Mode 2 M_DAM3 EQU 7 DMA Address Mode 3 M_DAM4 EQU 8 DMA Address Mode 4 M_DAM5 EQU 9 DMA Address Mode 5 M_D3D EQU 10 DMA Three Dimensional Mode M_DRS EQU F800 DMA Request Source Mas...

Page 343: ...H EQU E00 DMA Active Channel Mask DCH0DCH2 M_DCH0 EQU 9 DMA Active Channel 0 M_DCH1 EQU 10 DMA Active Channel 1 M_DCH2 EQU 11 DMA Active Channel 2 B 8 PHASE LOCKED LOOP PLL EQUATES Phase Locked Loop PLL equates Register Addresses Of PLL M_PCTL EQU FFFFFD PLL Control Register PLL Control Register M_MF EQU FFF Multiplication Factor Bit Mask MF0 MF11 M_DF EQU 7000 Division Factor Bit Mask DF0 DF2 M_X...

Page 344: ... BA3W0 BA3W3 M_BDFW EQU 1F0000 Default Area Wait Control Mask BDFW0 BDFW4 M_BBS EQU 21 Bus State M_BLH EQU 22 Bus Lock Hold M_BRH EQU 23 Bus Request Hold DRAM Control Register M_BCW EQU 3 In Page Wait States Bit Mask BCW0 BCW1 M_BRW EQU C Out Of Page Wait States Bit Mask BRW0 BRW1 M_BPS EQU 300 DRAM Page Size Bit Mask BPS0 BPS1 M_BPLE EQU 11 Page Logic Enable M_BME EQU 12 Mastership Enable M_BRE E...

Page 345: ... M_SM EQU 20 Arithmetic Saturation M_RM EQU 21 Rounding Mode M_CP0 EQU 22 bit 0 of priority bits in SR M_CP1 EQU 23 bit 1 of priority bits in SR control and status bits in OMR M_CDP EQU 300 mask for CORE DMA priority bits in OMR M_MA EQU 0 Operating Mode A M_MB EQU 1 Operating Mode B M_MC EQU 2 Operating Mode C M_MD EQU 3 Operating Mode D M_EBD EQU 4 External Bus Disable bit in OMR M_SD EQU 6 Stop...

Page 346: ...QU I_VEC 10 IRQA I_IRQB EQU I_VEC 12 IRQB I_IRQC EQU I_VEC 14 IRQC I_IRQD EQU I_VEC 16 IRQD DMA Interrupts I_DMA0 EQU I_VEC 18 DMA Channel 0 I_DMA1 EQU I_VEC 1A DMA Channel 1 I_DMA2 EQU I_VEC 1C DMA Channel 2 I_DMA3 EQU I_VEC 1E DMA Channel 3 I_DMA4 EQU I_VEC 20 DMA Channel 4 I_DMA5 EQU I_VEC 22 DMA Channel 5 Timer Interrupts I_TIM0C EQU I_VEC 24 TIMER 0 compare I_TIM0OF EQU I_VEC 26 TIMER 0 overf...

Page 347: ...tatus I_SI1RLS EQU I_VEC 44 ESSI1 Receive last slot I_SI1TD EQU I_VEC 46 ESSI1 Transmit data I_SI1TDE EQU I_VEC 48 ESSI1 Transmit Data With Exception Status I_SI1TLS EQU I_VEC 4A ESSI1 Transmit last slot SCI Interrupts I_SCIRD EQU I_VEC 50 SCI Receive Data I_SCIRDE EQU I_VEC 52 SCI Receive Data With Exception Status I_SCITD EQU I_VEC 54 SCI Transmit Data I_SCIIL EQU I_VEC 56 SCI Idle Line I_SCITM ...

Page 348: ...eric PHYSICAL_PIN_MAP string TQFP144 port DE_ inout bit SC02 inout bit SC01 inout bit SC00 inout bit STD0 inout bit SCK0 inout bit M O T O R O L A S S D T J T A G S O F T W A R E BSDL File Generated Mon Apr 8 10 13 47 1996 Revision History entity DSP56309 is generic PHYSICAL_PIN_MAP string TQFP144 port DE_ inout bit SC02 inout bit SC01 inout bit SC00 inout bit STD0 inout bit SCK0 inout bit ...

Page 349: ...ut bit STD1 inout bit SC10 inout bit SC11 inout bit SC12 inout bit TXD inout bit SCLK inout bit RXD inout bit TIO0 inout bit TIO1 inout bit TIO2 inout bit HAD inout bit_vector 0 to 7 HREQ inout bit MODD in bit MODC in bit MODB in bit MODA in bit D inout bit_vector 0 to 23 A out bit_vector 0 to 17 EXTAL in bit XTAL linkage bit RD_N out bit WR_N out bit AA out bit_vector 0 to 3 BR_N buffer bit BG_N ...

Page 350: ...to 3 JVCC linkage bit JGND1 linkage bit JGND linkage bit HACK inout bit HDS inout bit HRW inout bit CVCC linkage bit_vector 0 to 1 CGND linkage bit_vector 0 to 1 HCS inout bit HA9 inout bit HA8 inout bit HAS inout bit use STD_1149_1_1994 all attribute COMPONENT_CONFORMANCE of DSP56309 entity is ÒSTD_1149_1_1993Ó attribute PIN_MAP of DSP56309 entity is PHYSICAL_PIN_MAP constant TQFP144 PIN_MAP_STRI...

Page 351: ...CAS_N 52 Ò ÒXTAL 53 Ò ÒEXTAL 55 Ò ÒCVCC 57 65 Ò ÒCGND 58 66 Ò ÒCLKOUT 59 Ò ÒBCLK 60 Ò ÒBCLK_N 61 Ò ÒTA_N 62 Ò ÒBR_N 63 Ò ÒBB_N 64 Ò ÒWR_N 67 Ò ÒRD_N 68 Ò ÒBG_N 71 Ò ÒA 72 73 76 77 78 79 82 83 84 85 88 89 92 93 94 97 98 99 Ò ÒAVCC 74 80 86 95 Ò ÒAGND 75 81 87 96 Ò ÒD 100 101 102 105 106 107 108 109 110 113 114 115 116 117 Ò Ò 118 121 122 123 124 125 128 131 132 133 Ò ÒDVCC 103 111 119 129 Ò ÒDGND 1...

Page 352: ... is Ò0010Ó version Ò000110Ó manufacturerÕs use Ò0000000010Ó sequence number Ò00000001110Ó manufacturer identity Ò1Ó 1149 1 requirement attribute REGISTER_ACCESS of DSP56309 entity is ÒONCE 8 ENABLE_ONCE DEBUG_REQUEST Ó attribute BOUNDARY_LENGTH of DSP56309 entity is 144 attribute BOUNDARY_REGISTER of DSP56309 entity is num cell port func safe ccell dis rslt Ò0 BC_1 MODA input X Ó Ò1 BC_1 MODB inpu...

Page 353: ... 1 Z Ó Ò38 BC_1 A 10 output3 X 33 1 Z Ó Ò39 BC_1 A 9 output3 X 33 1 Z Ó num cell port func safe ccell dis rslt Ò40 BC_1 A 8 output3 X 43 1 Z Ó Ò41 BC_1 A 7 output3 X 43 1 Z Ó Ò42 BC_1 A 6 output3 X 43 1 Z Ó Ò43 BC_1 control 1 Ó Ò44 BC_1 A 5 output3 X 43 1 Z Ó Ò45 BC_1 A 4 output3 X 43 1 Z Ó Ò46 BC_1 A 3 output3 X 43 1 Z Ó Ò47 BC_1 A 2 output3 X 43 1 Z Ó Ò48 BC_1 A 1 output3 X 43 1 Z Ó Ò49 BC_1 A 0...

Page 354: ...ol 1 Ó Ò88 BC_6 HAD 7 bidir X 87 1 Z Ó Ò89 BC_1 control 1 Ó Ò90 BC_6 HAS bidir X 89 1 Z Ó Ò91 BC_1 control 1 Ó Ò92 BC_6 HA8 bidir X 91 1 Z Ó Ò93 BC_1 control 1 Ó Ò94 BC_6 HA9 bidir X 93 1 Z Ó Ò95 BC_1 control 1 Ó Ò96 BC_6 HCS bidir X 95 1 Z Ó Ò97 BC_1 control 1 Ó Ò98 BC_6 TIO0 bidir X 97 1 Z Ó Ò99 BC_1 control 1 Ó num cell port func safe ccell dis rslt Ò100 BC_6 TIO1 bidir X 99 1 Z Ó Ò101 BC_1 con...

Page 355: ...ontrol 1 Ó Ò135 BC_6 SC02 bidir X 134 1 Z Ó Ò136 BC_1 control 1 Ó Ò137 BC_6 STD1 bidir X 136 1 Z Ó Ò138 BC_1 control 1 Ó Ò139 BC_6 SRD1 bidir X 138 1 Z Ó num cell port func safe ccell dis rslt Ò140 BC_1 control 1 Ó Ò141 BC_6 SC11 bidir X 140 1 Z Ó Ò142 BC_1 control 1 Ó Ò143 BC_6 SC12 bidir X 142 1 Z Ó end DSP56309 TQFP M O T O R O L A S S D T J T A G S O F T W A R E BSDL File Generated Wed May 20 ...

Page 356: ...to 23 A out bit_vector 0 to 17 EXTAL in bit XTAL linkage bit RD_N out bit WR_N out bit AA out bit_vector 0 to 3 BR_N buffer bit BG_N in bit BB_N inout bit PCAP linkage bit RESET_N in bit PINIT in bit TA_N in bit CAS_N out bit BCLK out bit BCLK_N out bit CLKOUT buffer bit TRST_N in bit TDO out bit TDI in bit TCK in bit TMS in bit RESERVED linkage bit_vector 0 to 1 SGND linkage bit_vector 0 to 1 SVC...

Page 357: ...1149_1_1994 all attribute COMPONENT_CONFORMANCE of DSP56309 entity is ÒSTD_1149_1_1993Ó attribute PIN_MAP of DSP56309 entity is PHYSICAL_PIN_MAP constant TQFP144 PIN_MAP_STRING ÒSRD1 1 Ò ÒSTD1 2 Ò ÒSC02 3 Ò ÒSC01 4 Ò ÒDE_N 5 Ò ÒPINIT 6 Ò ÒSRD0 7 Ò ÒSVCC 8 25 Ò ÒSGND 9 26 Ò ÒSTD0 10 Ò ÒSC10 11 Ò ÒSC00 12 Ò ÒRXD 13 Ò ÒTXD 14 Ò ÒSCLK 15 Ò ÒSCK1 16 Ò ÒSCK0 17 Ò ÒQVCC 18 56 91 126 Ò ÒQGND 19 54 90 127 ...

Page 358: ...81 87 96 Ò ÒD 100 101 102 105 106 107 108 109 110 113 114 115 116 117 118 121 Ò Ò122 123 124 125 128 131 132 133 Ò ÒDVCC 103 111 119 129 Ò ÒDGND 104 112 120 130 Ò ÒMODD 134 Ò ÒMODC 135 Ò ÒMODB 136 Ò ÒMODA 137 Ò ÒTRST_N 138 Ò ÒTDO 139 Ò ÒTDI 140 Ò ÒTCK 141 Ò ÒTMS 142 Ò ÒSC12 143 Ò ÒSC11 144 Ò attribute TAP_SCAN_IN of TDI signal is true attribute TAP_SCAN_OUT of TDO signal is true attribute TAP_SCAN...

Page 359: ...t Ò0 BC_1 MODA input X Ó Ò1 BC_1 MODB input X Ó Ò2 BC_1 MODC input X Ó Ò3 BC_1 MODD input X Ó Ò4 BC_6 D 23 bidir X 13 1 Z Ó Ò5 BC_6 D 22 bidir X 13 1 Z Ó Ò6 BC_6 D 21 bidir X 13 1 Z Ó Ò7 BC_6 D 20 bidir X 13 1 Z Ó Ò8 BC_6 D 19 bidir X 13 1 Z Ó Ò9 BC_6 D 18 bidir X 13 1 Z Ó Ò10 BC_6 D 17 bidir X 13 1 Z Ó Ò11 BC_6 D 16 bidir X 13 1 Z Ó Ò12 BC_6 D 15 bidir X 13 1 Z Ó Ò13 BC_1 control 1 Ó Ò14 BC_6 D 1...

Page 360: ...43 1 Z Ó Ò48 BC_1 A 1 output3 X 43 1 Z Ó Ò49 BC_1 A 0 output3 X 43 1 Z Ó Ò50 BC_1 BG_N input X Ó Ò51 BC_1 AA 0 output3 X 55 1 Z Ó Ò52 BC_1 AA 1 output3 X 56 1 Z Ó Ò53 BC_1 RD_N output3 X 64 1 Z Ó Ò54 BC_1 WR_N output3 X 64 1 Z Ó Ò55 BC_1 control 1 Ó Ò56 BC_1 control 1 Ó Ò57 BC_1 control 1 Ó Ò58 BC_6 BB_N bidir X 57 1 Z Ó Ò59 BC_1 BR_N output2 X Ó num cell port func safe ccell dis rslt Ò60 BC_1 TA_...

Page 361: ...e ccell dis rslt Ò100 BC_6 TIO1 bidir X 99 1 Z Ó Ò101 BC_1 control 1 Ó Ò102 BC_6 TIO2 bidir X 101 1 Z Ó Ò103 BC_1 control 1 Ó Ò104 BC_6 HREQ bidir X 103 1 Z Ó Ò105 BC_1 control 1 Ó Ò106 BC_6 HACK bidir X 105 1 Z Ó Ò107 BC_1 control 1 Ó Ò108 BC_6 HRW bidir X 107 1 Z Ó Ò109 BC_1 control 1 Ó Ò110 BC_6 HDS bidir X 109 1 Z Ó Ò111 BC_1 control 1 Ó Ò112 BC_6 SCK0 bidir X 111 1 Z Ó Ò113 BC_1 control 1 Ó Ò...

Page 362: ...C11 bidir X 140 1 Z Ó Ò142 BC_1 control 1 Ó Ò143 BC_6 SC12 bidir X 142 1 Z Ó end DSP56309 M O T O R O L A S S D T J T A G S O F T W A R E BSDL File Generated Wed May 20 09 48 32 1998 Revision History entity DSP56309 is generic PHYSICAL_PIN_MAP string ÒPBGA196Ó port DE_N inout bit SC02 inout bit SC01 inout bit SC00 inout bit STD0 inout bit SCK0 inout bit SRD0 inout bit SRD1 inout bit SCK1 inout bit...

Page 363: ... bit_vector 0 to 4 SVCC linkage bit_vector 0 to 1 HVCC linkage bit DVCC linkage bit_vector 0 to 3 AVCC linkage bit_vector 0 to 2 HACK inout bit HDS inout bit HRW inout bit CVCC linkage bit_vector 0 to 1 HCS inout bit HA9 inout bit HA8 inout bit HAS inout bit GND linkage bit_vector 0 to 63 QVCCL linkage bit_vector 0 to 3 QVCCH linkage bit_vector 0 to 2 PVCC linkage bit PGND linkage bit PGND1 linkag...

Page 364: ... Ò ÒGND E8 E9 E10 E11 F4 F5 F11 G4 G5 G6 G7 G8 G9 G10 G11 H4 H5 H6 Ò ÒH7 H8 H9 H10 H11 J4 J5 J6 J7 J8 J9 J10 J11 K4 K5 K6 K7 K8 K9 Ò ÒK10 K11 L4 L5 L6 L7 L8 L9 L10 L11 D4 D5 D6 D7 D8 D9 D10 D11 E4 Ò ÒE5 E6 E7 F6 F7 F8 F9 F10 Ò ÒSTD0 E1 Ò ÒSVCC E2 K1 Ò ÒSRD0 E3 Ò ÒA N14 M13 M14 L13 L14 K13 K14 J13 J12 J14 H13 H14 G14 G12 F13 F14 Ò ÒE13 E12 Ò ÒRXD F1 Ò ÒSC10 F2 Ò ÒSC00 F3 Ò ÒQVCCH F12 H1 M7 Ò ÒSCK1 ...

Page 365: ...N_RESET of TRST_N signal is true attribute TAP_SCAN_CLOCK of TCK signal is 20 0e6 BOTH attribute INSTRUCTION_LENGTH of DSP56309 entity is 4 attribute INSTRUCTION_OPCODE of DSP56309 entity is ÒEXTEST 0000 Ó ÒSAMPLE 0001 Ó ÒIDCODE 0010 Ó ÒCLAMP 0101 Ó ÒHIGHZ 0100 Ó ÒENABLE_ONCE 0110 Ó ÒDEBUG_REQUEST 0111 Ó ÒBYPASS 1111 Ó attribute INSTRUCTION_CAPTURE of DSP56309 entity is Ò0001Ó attribute IDCODE_REG...

Page 366: ...ort func safe ccell dis rslt Ò20 BC_6 D 8 bidir X 26 1 Z Ó Ò21 BC_6 D 7 bidir X 26 1 Z Ó Ò22 BC_6 D 6 bidir X 26 1 Z Ó Ò23 BC_6 D 5 bidir X 26 1 Z Ó Ò24 BC_6 D 4 bidir X 26 1 Z Ó Ò25 BC_6 D 3 bidir X 26 1 Z Ó Ò26 BC_1 control 1 Ó Ò27 BC_6 D 2 bidir X 26 1 Z Ó Ò28 BC_6 D 1 bidir X 26 1 Z Ó Ò29 BC_6 D 0 bidir X 26 1 Z Ó Ò30 BC_1 A 17 output3 X 33 1 Z Ó Ò31 BC_1 A 16 output3 X 33 1 Z Ó Ò32 BC_1 A 15 ...

Page 367: ...ut X Ó Ò69 BC_1 CAS_N output3 X 65 1 Z Ó Ò70 BC_1 AA 2 output3 X 66 1 Z Ó Ò71 BC_1 AA 3 output3 X 67 1 Z Ó Ò72 BC_1 RESET_N input X Ó Ò73 BC_1 control 1 Ó Ò74 BC_6 HAD 0 bidir X 73 1 Z Ó Ò75 BC_1 control 1 Ó Ò76 BC_6 HAD 1 bidir X 75 1 Z Ó Ò77 BC_1 control 1 Ó Ò78 BC_6 HAD 2 bidir X 77 1 Z Ó Ò79 BC_1 control 1 Ó num cell port func safe ccell dis rslt Ò80 BC_6 HAD 3 bidir X 79 1 Z Ó Ò81 BC_1 contro...

Page 368: ... BC_6 TXD bidir X 117 1 Z Ó Ò119 BC_1 control 1 Ó num cell port func safe ccell dis rslt Ò120 BC_6 RXD bidir X 119 1 Z Ó Ò121 BC_1 control 1 Ó Ò122 BC_6 SC00 bidir X 121 1 Z Ó Ò123 BC_1 control 1 Ó Ò124 BC_6 SC10 bidir X 123 1 Z Ó Ò125 BC_1 control 1 Ó Ò126 BC_6 STD0 bidir X 125 1 Z Ó Ò127 BC_1 control 1 Ó Ò128 BC_6 SRD0 bidir X 127 1 Z Ó Ò129 BC_1 PINIT input X Ó Ò130 BC_1 control 1 Ó Ò131 BC_6 D...

Page 369: ...C 22 DSP56309UM D MOTOROLA DSP56309 BSDL Listing ...

Page 370: ...MOTOROLA DSP56309UM D D 1 APPENDIX D PROGRAMMING REFERENCE ...

Page 371: ...RY MAP D 4 D 3 INTERRUPT ADDRESSES AND SOURCES D 11 D 4 INTERRUPT PRIORITIES D 13 D 5 PROGRAMMING REFERENCE CENTRAL PROCESSOR D 15 PLL D 19 HOST INTERFACE HI08 D 20 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI D 26 SERIAL COMMUNICATIONS INTERFACE D 30 TIMERS D 33 GENERAL PURPOSE I O GPIO D 36 ...

Page 372: ...sheet provides room to write in the value of each bit and the hexadecimal value for each register The programmer can photocopy these sheets and reuse them for each application development project For details about the instruction set of the DSP56300 family chips see the DSP56300 Family Manual D 1 1 Peripheral Addresses Table D 1 lists the memory addresses of all on chip peripherals D 1 2 Interrupt...

Page 373: ...FFFFA DRAM Control Register DCR FFF9 FFFFF9 Address Attribute Register 0 AAR0 FFF8 FFFFF8 Address Attribute Register 1 AAR1 FFF7 FFFFF7 Address Attribute Register 2 AAR2 FFF6 FFFFF6 Address Attribute Register 3 AAR3 FFF5 FFFFF5 ID Register IDR DMA FFF4 FFFFF4 DMA Status Register DSTR FFF3 FFFFF3 DMA Offset Register 0 DOR0 FFF2 FFFFF2 DMA Offset Register 1 DOR1 FFF1 FFFFF1 DMA Offset Register 2 DOR...

Page 374: ...3 FFFFE3 DMA Source Address Register DSR3 FFE2 FFFFE2 DMA Destination Address Register DDR3 FFE1 FFFFE1 DMA Counter DCO3 FFE0 FFFFE0 DMA Control Register DCR3 DMA4 FFDF FFFFDF DMA Source Address Register DSR4 FFDE FFFFDE DMA Destination Address Register DDR4 FFDD FFFFDD DMA Counter DCO4 FFDC FFFFDC DMA Control Register DCR4 DMA5 FFDB FFFFDB DMA Source Address Register DSR5 FFDA FFFFDA DMA Destinat...

Page 375: ...served FFCA FFFFCA Reserved PORT B FFC9 FFFFC9 Host Port GPIO Data Register HDR FFC8 FFFFC8 Host Port GPIO Direction Register HDDR HI08 FFC7 FFFFC7 Host Transmit Register HTX FFC6 FFFFC6 Host Receive Register HRX FFC5 FFFFC5 Host Base Address Register HBAR FFC4 FFFFC4 Host Polarity Control Register HPCR FFC3 FFFFC3 Host Status Register HSR FFC2 FFFFC2 Host Control Register HCR FFC1 FFFFC1 Reserved...

Page 376: ...egister RX0 FFB7 FFFFB7 ESSI 0 Status Register SSISR0 FFB6 FFFFB6 ESSI 0 Control Register B CRB0 FFB5 FFFFB5 ESSI 0 Control Register A CRA0 FFB4 FFFFB4 ESSI 0 Transmit Slot Mask Register A TSMA0 FFB3 FFFFB3 ESSI 0 Transmit Slot Mask Register B TSMB0 FFB2 FFFFB2 ESSI 0 Receive Slot Mask Register A RSMA0 FFB1 FFFFB1 ESSI 0 Receive Slot Mask Register B RSMB0 Ñ FFB0 FFFFB0 Reserved PORT D FFAF FFFFAF ...

Page 377: ...SSI 1 Control Register B CRB1 FFA5 FFFFA5 ESSI 1 Control Register A CRA1 FFA4 FFFFA4 ESSI 1 Transmit Slot Mask Register A TSMA1 FFA3 FFFFA3 ESSI 1 Transmit Slot Mask Register B TSMB1 FFA2 FFFFA2 ESSI 1 Receive Slot Mask Register A RSMA1 FFA1 FFFFA1 ESSI 1 Receive Slot Mask Register B RSMB1 Ñ FFA0 FFFFA0 Reserved PORT E FF9F FFFF9F Port E Control Register PCRE FF9E FFFF9E Port E Direction Register ...

Page 378: ... FFFF98 SCI Recieve Data Register Low SRXL FF97 FFFF97 SCI Transmit Data Register High STXH FF96 FFFF96 SCI Transmit Data Register Middle STXM FF95 FFFF95 SCI Transmit Data Register Low STXL FF94 FFFF94 SCI Transmit Address Register STXA FF93 FFFF93 SCI Status Register SSR Ñ FF92 FFFF92 Reserved FF91 FFFF91 Reserved FF90 FFFF90 Reserved Table D 1 Internal I O Memory Map Continued Peripheral 16 Bit...

Page 379: ...d Register TLR1 FF89 FFFF89 Timer 1 Compare Register TCPR1 FF88 FFFF88 Timer 1 Count Register TCR1 FF87 FFFF87 Timer 2 Control Status Register TCSR2 FF86 FFFF86 Timer 2 Load Register TLR2 FF85 FFFF85 Timer 2 Compare Register TCPR2 FF84 FFFF84 Timer 2 Count Register TCR2 FF83 FFFF83 Timer Prescaler Load Register TPLR FF82 FFFF82 Timer Prescaler Count Register TPCR Ñ FF81 FFFF81 Reserved FF80 FFFF80...

Page 380: ... Reserved VBA 0E 3 Reserved VBA 10 0Ð2 IRQA VBA 12 0Ð2 IRQB VBA 14 0Ð2 IRQC VBA 16 0Ð2 IRQD VBA 18 0Ð2 DMA Channel 0 VBA 1A 0Ð2 DMA Channel 1 VBA 1C 0Ð2 DMA Channel 2 VBA 1E 0Ð2 DMA Channel 3 VBA 20 0Ð2 DMA Channel 4 VBA 22 0Ð2 DMA Channel 5 VBA 24 0Ð2 TIMER 0 Compare VBA 26 0Ð2 TIMER 0 Overflow VBA 28 0Ð2 TIMER 1 Compare VBA 2A 0Ð2 TIMER 1 Overflow VBA 2C 0Ð2 TIMER 2 Compare VBA 2E 0Ð2 TIMER 2 Ov...

Page 381: ...h Exception Status VBA 4A 0Ð2 ESSI1 Transmit Last Slot VBA 4C 0Ð2 Reserved VBA 4E 0Ð2 Reserved VBA 50 0Ð2 SCI Receive Data VBA 52 0Ð2 SCI Receive Data With Exception Status VBA 54 0Ð2 SCI Transmit Data VBA 56 0Ð2 SCI Idle Line VBA 58 0Ð2 SCI Timer VBA 5A 0Ð2 Reserved VBA 5C 0Ð2 Reserved VBA 5E 0Ð2 Reserved VBA 60 0Ð2 Host Receive Data Full VBA 62 0Ð2 Host Transmit Data Empty VBA 64 0Ð2 Host Comman...

Page 382: ...terrupt Ñ Trap Lowest Non Maskable Interrupt Levels 0 1 2 Maskable Highest IRQA External Interrupt Ñ IRQB External Interrupt Ñ IRQC External Interrupt Ñ IRQD External Interrupt Ñ DMA Channel 0 Interrupt Ñ DMA Channel 1 Interrupt Ñ DMA Channel 2 Interrupt Ñ DMA Channel 3 Interrupt Ñ DMA Channel 4 Interrupt Ñ DMA Channel 5 Interrupt Ñ Host Command Interrupt Ñ Host Transmit Data Empty Ñ Host Receive ...

Page 383: ...ive Last Slot Interrupt Ñ ESSI1 TX Data With Exception Interrupt Ñ ESSI1 Transmit Last Slot Interrupt Ñ ESSI1 TX Data Interrupt Ñ SCI Receive Data With Exception Interrupt Ñ SCI Receive Data Ñ SCI Transmit Data Ñ SCI Idle Line Ñ SCI Timer Ñ TIMER0 Overflow Interrupt Ñ TIMER0 Compare Interrupt Ñ TIMER1 Overflow Interrupt Ñ TIMER1 Compare Interrupt Ñ TIMER2 Overflow Interrupt Lowest TIMER2 Compare I...

Page 384: ... 00 01 10 11 None IPL 0 IPL 0 1 IPL 0 1 2 Carry Overßow Zero Negative Unnormalized U Acc 47 xnor Acc 46 Extension Limit FFT Scaling S Acc 46 xor Acc 45 Reserved Sixteen Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO Forever Flag Sixteenth Bit Arithmetic Reserved Instruction Cache Enable Arithmetic Saturation Rounding Mode Core Priority CP 1 0 Core Priority 00 01 10 11 0 lowest 1 2...

Page 385: ...12 11 10 9 8 7 6 5 4 3 2 1 0 EBD MC MB MA 19 18 17 16 23 22 21 20 SD BRT TAS SEN CDP1 CDP0 WRP EOV EUN XYS BE MD Core DMA Priority CDP 1 0 Core DMA Priority 00 01 10 11 Core vs DMA Priority DMA accesses Core DMA accesses Core DMA accesses Core 0 0 0 0 0 0 0 Chip Operating Mode Register COM System Stack Control Status Register SCS Extended Chip Operating Mode Register COM X Latched from levels on M...

Page 386: ...er IPRÐC 23 22 21 20 19 18 16 17 D1L1 IAL2 Trigger 0 Level 1 Neg Edge IRQA Mode IAL1 IAL0 Enabled IPL 0 0 No Ñ 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 IBL2 Trigger 0 Level 1 Neg Edge IRQB Mode IBL1 IBL0 Enabled IPL 0 0 No Ñ 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 ICL0 ICL1 ICL2 IDL0 D2L0 D2L1 D3L0 D3L1 D4L0 D4L1 D5L0 D5L1 ICL2 Trigger 0 Level 1 Neg Edge IRQC Mode ICL1 ICL0 Enabled IPL 0 0 No Ñ 0 1 Yes 0 1 0 Yes 1 1 1...

Page 387: ...Register IPRÐP HPL1 HPL0 Enabled IPL 0 0 No Ñ 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 Host IPL S0L1 S0L0 Enabled IPL 0 0 No Ñ 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 ESSI0 IPL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S1L1 S1L0 SOL1 S0L0 HPL1 HPL0 23 22 21 20 19 18 16 17 SCL0 SCL1 T0L0 T0L1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S1L1 S1L0 Enabled IPL 0 0 No Ñ 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 ESSI1 IPL SCL1 SCL0 Enabled IPL 0 0 N...

Page 388: ...llator 1 EXTAL Driven From An External Source Clock Output Disable COD 0 50 Duty Cycle Clock 1 Pin Held In High State Crystal Range Bit XTLR 0 External Xtal Freq 200KHz 1 External Xtal Freq 200KHz Predivision Factor Bits PD0 Ð PD3 PD3 Ð PD0 Predivision Factor PDF 0 1 2 F 1 2 3 16 Multiplication Factor Bits MF0 Ð MF11 MF11 Ð MF0 Multiplication Factor MF 000 001 002 FFF FFF 1 2 3 4095 4096 PSTP and ...

Page 389: ...16 23 22 21 20 Receive High Byte Receive Middle Byte Receive Low Byte Host Receive Data Register HRX X FFEC6 Read Only Reset empty Host Receive Data usually Read by program 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 23 22 21 20 Transmit High Byte Transmit Middle Byte Transmit Low Byte Host Transmit Data usually Loaded by program Host Transmit Data Register HTX X FFEC7 Write Only Reset empty...

Page 390: ...HF0 Host Flags Read Only Host Command Pending 1 Ready 0 Wait Host Transmit Data Empty 1 Write 0 Wait 0 Host Staus Register HSR X FFFFC3 Read Only Reset 2 7 6 5 4 3 2 1 0 15 0 0 0 Host Receive Interrupt Enable 1 Enable 0 Disable HCIE HRIE HF3 HTIE HF2 Host Flag 2 Host Command Interrupt Enable Host Transmit Interrupt Enable 1 Enable 0 Disable 0 Host Control Register HCR X FFFFC2 Read Write Reset 0 i...

Page 391: ...st Address Line 9 Enable 0 HA9 GPIO 1 HA9 HA9 Host Address Line 8 Enable 0 HA8 GPIO 1 HA8 HA8 Host GPIO Port Enable 0 GPIO Pins Disable 1 GPIO Pin Enable Host Acknowledge Priority 0 HACK Active Low 1 HACK Active High Host Chip Select Polarity 0 HCS Active Low Host Dual Data Strobe 0 Singles Stroke 1 Dual Stoke Host Multiplexed Bus 0 Nonmultiplexed 1 Multiplexed Host Address Strobe Polarity 0 Strob...

Page 392: ...lize Write Only Host Little Endian Receive Request Enable DMA Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 Host DSP 1 DSP Host 0 No Action 1 Initialize DMA HDRQ 0 HDRQ HREQ HTRQ HACK HRRQ 0 HREQ HACK 1 HTRQ HRRQ Reset 0 7 6 5 4 3 2 1 0 Reserved Program as 0 0 RXDF HF3 TXDE HF2 HREQ DMA TRDY Interrupt Status Register ISR 2 Read Write Reset 06 Transmit Data Register Empty 0 Wait 1 Write T...

Page 393: ... 3 2 1 0 IV0 IV4 IV1 IV3 IV7 IV5 Interrupt Vector Register IVR IV2 Reset 0F Contains the interrupt vector or number IV6 7 6 5 4 3 2 1 0 HC0 HC4 HC1 HC3 HC7 HC5 Command Vector Register CVR HC2 Reset 2A Contains the host command interrupt address HC6 Host Vector Contains Host Command Interrupt Address Ö 2 Host Command Handshakes Executing Host Command Interrupts ...

Page 394: ...ata usually Read by program Receive Byte Registers 7 6 5 4 Read Only Reset 00 Transmit Byte Registers 7 6 5 4 Write Only Reset 00 Receive Byte Registers 6 5 4 0 0 0 0 0 0 0 0 0 7 7 Receive Middle Byte Receive High Byte Not Used Receive Low Byte 7 0 7 0 0 7 Host Transmit Data usually loaded by program 6 5 4 0 0 0 0 0 0 0 0 0 7 7 Transmit Middle Byte Transmit High Byte Not Used Transmit Low Byte ...

Page 395: ...bits 1 0 1 32 data in last 24 bits 1 1 0 Reserved 1 1 1 Reserved ESSI Control Register A CRAx ESSI0 FFFFB5 Read Write ESSI1 FFFFA5 Read Write Reset 000000 Select SC1 as Tx 0 drive enable 0 SC1 functions as serial I O flag 1 functions as driver enable of Tx 0 external buffer Frame Rate Divider Control DC4 0 00 1F 1 to 32 Divide ratio for Normal mode of time slots for Network Prescaler Range 0 Ö8 1 ...

Page 396: ...n rising in on falling 1 in on rising out on falling Sync Async Control Tx Rx transfer together or not 0 Asynchronous 1 Synchronous ESSI Control Register B CRBx ESSI0 FFFFB6 Read Write ESSI1 FFFFA6 Read Write Reset 000000 Transmit 1 Enable SYN 1 only 0 Disable 1 Enable Transmit Interrupt Enable 0 Disable 1 Enable Receive Interrupt Enable 0 Disable 1 Enable Transmit Last Slot Interrupt Enable 0 Dis...

Page 397: ...1 Frame Sync Occurred Transmitter Underrun Error Flag 0 OK 1 Error Receiver Overrun Error Flag 0 OK 1 Error Transmit Data Register Empty 0 Wait 1 Write Transmit Frame Sync 0 Sync Inactive 1 Sync Active Receive Data Register Full 1 Read Serial Input Flag 0 If SCD0 0 SYN 1 TE1 0 latch SC0 on FS Serial Input Flag 1 If SCD1 0 SYN 1 TE2 0 latch SC0 on FS 0 Wait SSI Status Bits SSI Status Register SSISR...

Page 398: ...ESSI1 FFFFA3 Read Write Reset FFFF ESSI Receive Slot Mask A ESSI Receive Slot Mask B ESSI Transmit Slot Mask A ESSI Transmit Slot Mask B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RS7 RS5 RS4 RS3 RS2 RS1 RS0 16 23 Reserved Program as 0 RS6 0 RS15 RS14 RS13 RS12 RS11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TS23 TS21 TS20 TS19 TS18 TS17 TS16 16 23 Reserved Program as 0 TS22 0 TS31 TS30 TS29 TS28 TS27 15 14...

Page 399: ...hronous 1 Start 8 Data 1 Stop 0 1 1 Reserved 1 0 0 11 bit Asynchronous 1 Start 8 Data Even Parity 1 Stop 1 0 1 11 bit Asynchronous 1 Start 8 Data Odd Parity 1 Stop 1 1 0 11 bit Multidrop 1 Start 8 Data Data Type 1 Stop 1 1 1 Reserved Transmitter Enable 0 Transmitter Disable 1 Transmitter Enable Transmit Interrupt Enable 0 Transmit Interrupts Disabled 1 Transmit Interrupts Enabled Idle Line Interru...

Page 400: ...ull 0 Receive Data Register Empty 1 Receive Data Register Full Transmitter Data Register Empty 0 Transmitter Data Register full 1 Transmitter Data Register empty Transmitter Empty 0 Transmitter full 1 Transmitter empty Clock Divider Bits CD11 Ð CD0 CD11 Ð CD0 Icyc Rate 000 Icyc 1 001 Icyc 2 002 Icyc 3 FFE Icyc 4095 FFF Icyc 4096 SCI Clock Prescaler 0 Ö1 1 Ö 8 SCI Status Register SSR Clock Out Divi...

Page 401: ...ers Address X FFFF95 Ð X FFFF97 Write Reset xxxxxx Unpacking TXD SCI Transmit SR SCI Transmit Data Registers SCI Receive Data Registers X FFFF94 STXA 23 16 15 8 7 0 SRX SRX SRX ÒAÓ ÒBÓ ÒCÓ Packing RXD SCI Receive SR SCI Receive Data Registers Address X FFFF98 Ð X FFFF9A Read Reset xxxxxx X FFFF9A X FFFF99 X FFFF98 Note STX is the same register decoded at four different addresses Note STX is the sa...

Page 402: ...22 21 20 PS0 PS1 0 Prescaler Preload Value PL 0 20 Reserved Program as 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 23 22 21 20 0 Current Value of Prescaler Counter PC 0 20 Timer Prescaler Load Register TPLR FFFF83 Read Write Reset 000000 Timer Prescaler Count Register TPCR FFFF82 Read Only Reset 000000 Reserved Program as 0 PS 1 0 Prescaler Clock Source 00 Internal CLK 2 01 TIO0 10 TIO1 11...

Page 403: ...0 Ð TC3 TC 3 0 TIO Clock Mode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 GPIO Output Output Input Input Input Input Output Ð Output Output Ð Ð Ð Ð Ð Internal Internal Internal External Internal Internal Internal Internal Ð Internal Internal Ð Ð Ð Ð Ð Timer Timer Pulse Timer Toggle Event Counter Input Width Input Period Capture Pulse Width Modulation Reserved Wa...

Page 404: ...R0 FFFF8E Write Only Reset 000000 TLR1 FFFF8A Write Only TLR2 FFFF86 Write Only Timer Compare Register TCPR0 FFFF8D Read Write Reset 000000 TCPR1 FFFF89 Read Write TCPR2 FFFF85 Read Write Timer Count Register TCR0 FFFF8C Read Only TCR1 FFFF88 Read Only TCR2 FFFF84 Read Only Reset 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 23 22 21 20 Value Compared to Counter Value 15 14 13 12 11 10 ...

Page 405: ......

Page 406: ... configured as ESSI PCn 0 Port Pin configured as GPIO Port C ESSI0 23 6 5 4 3 2 1 0 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 Port C Direction Register X FFFFBE Reset 0 PRRC ReadWrite 0 0 PDCn 1 Port Pin is Output PDCn 0 Port Pin is Input 23 6 5 4 3 2 1 0 PD5 PD4 PD3 PD2 PD1 PD0 Port C GPIO Data Register X FFFFBD Reset 0 PDRC ReadWrite 0 0 port pin n is GPIO input then PDn reflects the value on port pin n if ...

Page 407: ... configured as ESSI PCn 0 Port Pin configured as GPIO Port D ESSI1 23 6 5 4 3 2 1 0 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 Port D Direction Register X FFFFAE Reset 0 PRRD ReadWrite 0 0 PDCn 1 Port Pin is Output PDCn 0 Port Pin is Input 23 6 5 4 3 2 1 0 PD5 PD4 PD3 PD2 PD1 PD0 Port D GPIO Data Register X FFFFAD Reset 0 PDRD ReadWrite 0 0 port pin n is GPIO input then PDn reflects the value on port pin n if ...

Page 408: ... configured as SCI PCn 0 Port Pin configured as GPIO Port E SCI 23 6 5 4 3 2 1 0 PDC2 PDC1 PDC0 Port E Direction Register X FFFF9E Reset 0 PRRE ReadWrite 0 0 PDCn 1 Port Pin is Output PDCn 0 Port Pin is Input 23 6 5 4 3 2 1 0 PD2 PD1 PD0 Port E GPIO Data Register X FFFF9D Reset 0 PDRE ReadWrite 0 0 port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO output then...

Page 409: ......

Page 410: ... BT0ÐBT1 10 14 Breakpoint 0 Condition Code Select bits CC00ÐCC01 10 13 Breakpoint 0 Read Write Select bits RW00ÐRW01 10 12 Breakpoint 1 Condition Code Select bits CC10ÐCC11 10 14 Breakpoint 1 Read Write Select bits RW10ÐRW11 10 13 BSDL listing PBGA C 8 TQFP C 2 BSR register 11 7 BT0ÐBT1 bits 10 14 bus address 2 4 data 2 4 external address 2 9 external data 2 9 multiplexed 2 4 non multiplexed 2 4 b...

Page 411: ...e bit TE0 7 24 bit 17ÑESSI Receive Enable bit RE 7 26 bit 18ÑESSI Transmit Interrupt Enable bit TIE 7 26 bit 19ÑESSI Receive Interrupt Enable bit RIE 7 26 bit 20ÑESSI Transmit Last Slot Interrupt Enable bit TLIE 7 26 bit 21ÑESSI Receive Last Slot Interrupt Enable bit RLIE 7 27 bit 22ÑESSI Transmit Exception Interrupt Enable bit TEIE 7 27 bit 23ÑESSI Receive Exception Interrupt Enable bit REIE 7 27...

Page 412: ...tus Register SSISR 7 27 ESSI Time Slot Register TSR 7 34 ESSI Transmit 0 Enable bit TE0 7 24 ESSI Transmit 1 Enable bit TE1 7 23 ESSI Transmit 2 Enable bit TE2 7 22 ESSI Transmit Data registers TX2 TX1 TX0 7 34 ESSI Transmit Exception Interrupt Enable bit TEIE 7 27 ESSI Transmit Interrupt Enable bit TIE 7 26 ESSI Transmit Last Slot Interrupt Enable bit TLIE 7 26 ESSI Transmit Shift Registers 7 33 ...

Page 413: ...rupt Enable bit HCIE 6 10 bits 3 4ÑHost Flag 2 and 3 bits HF2 HF3 6 10 reserved bitsÑbits 5Ð15 6 10 HCS signal 2 21 HCSEN bit 6 13 HCSP bit 6 16 HDDR register 6 17 HDDS bit 6 15 HDR register 6 17 HDRQ bit 6 23 HDS signal 2 20 HDSP bit 6 14 HEN bit 6 14 HF0 bit 6 24 HF0 HF1 bits 6 11 HF1 bit 6 24 HF2 bit 6 27 HF2 HF3 bits 6 10 HF3 bit 6 27 HGEN bit 6 13 HI08 1 16 2 3 2 4 2 16 2 18 2 19 2 21 6 3 GPI...

Page 414: ...Host Flag 0 and 1 bits HF0 HF1 6 11 Host Flag 0 bit HF0 6 24 Host Flag 1 bit HF1 6 24 Host Flag 2 and 3 bits HF2 HF3 6 10 Host Flag 2 bit HF2 6 27 Host Flag 3 bit HF3 6 27 Host GPIO Port Enable bit HGEN 6 13 Host Interface 1 16 2 3 2 4 2 16 2 18 2 19 2 21 6 3 Host Little Endian bit HLEND 6 24 Host Multiplexed Bus bit HMUX 6 15 host port configuration 2 17 usage considerations 2 16 Host Port Contro...

Page 415: ...8 11 IF0 bit 7 28 IF1 bit 7 28 ILIE bit 8 11 IME bit 10 8 instruction cache 3 3 location 3 8 instruction set 1 7 Interface Control Register ICR 6 22 Interface Status Register ISR 6 26 Interface Vector Register IVR 6 28 internal buses 1 13 interrupt 1 10 ESSI 7 37 priority levels 4 12 servicing on HI08 6 32 sources 4 9 interrupt and mode control 2 3 2 14 2 15 interrupt control 2 14 2 15 interrupt e...

Page 416: ...ode select B signal 2 15 mode select C signal 2 15 mode select D signal 2 16 modulo adder 1 9 multiplexed bus 2 4 Multiplication Factor bits MF 4 18 multiplier accumulator MAC 1 8 1 9 N non maskable interrupt 2 8 2 9 non multiplexed bus 2 4 O OBCR register 10 12 bits 0Ð1ÑMemory Breakpoint Select bits MBS0ÐMBS1 10 12 bits 2Ð3ÑBreakpoint 0 Read Write Select bits RW00ÐRW01 10 12 bits 4Ð5ÑBreakpoint 0...

Page 417: ...e select signal TMS 2 36 OnCE JTAG port 2 3 On Chip Emulation OnCE module 1 12 On Chip Emulation module 10 3 on chip memory 1 12 program 3 6 X data RAM 3 6 Y data RAM 3 7 OPABDR register 10 20 OPABEX register 10 20 OPABFR register 10 20 OPDBR register 10 19 Operating 4 3 operating mode 4 3 bootstrap from byte wide external memory 4 7 bootstrap thorugh HI08 68302 68360 4 9 bootstrap through HI08 IS...

Page 418: ...rt C 1 signal PC1 2 25 port C 2 signal PC2 2 25 port C 3 signal PC3 2 26 port C 4 signal PC4 2 26 port C 5 signal PC5 2 27 Port C Control Register PCRC 7 43 Port C Data Register PDRC 7 45 Port C Direction Register PRRC 7 44 Port D 2 3 2 4 2 28 5 4 port D 0 signal PD0 2 28 port D 1 signal PD1 2 28 port D 2 signal PD2 2 29 port D 3 signal PD3 2 30 port D 4 signal PD4 2 30 port D 5 signal PD5 2 31 Po...

Page 419: ...est Enable bit RREQ 6 23 Receive Shift Register 7 33 Receive Slot Mask Registers RSMA RSMB 7 35 Received Bit 8 Address bit R8 8 15 Receiver Enable bit RE 8 10 Receiver Overrun Error Flag bit ROE 7 29 Receiver Wakeup Enable bit SBK 8 9 Register Select bits RS0ÐRS4 10 5 REIE bit 7 27 8 13 reserved bits in CRA register 7 11 7 13 7 14 in HBAR register bits 5Ð15 6 12 in HCR register bits 5Ð15 6 10 in H...

Page 420: ...17 SCR register bits 0 2ÑWord Select bits WDS0 WDS2 8 8 bit 3ÑSCI Shift Direction bit SSFTD 8 9 bit 4ÑSend Break bit SBK 8 9 bit 5ÑWakeup Mode Select bit WAKE 8 9 bit 6ÑReceiver Wakeup Enable bit RWU 8 9 bit 7ÑWired OR Mode Select bit WOMS 8 10 bit 8ÑReceiver Enable bit RE 8 10 bit 9ÑTransmitter Enable bit TE 8 10 bit 10ÑIdle Line Interrupt Enable bit ILIE 8 11 bit 11ÑReceive Interrupt Enable bit ...

Page 421: ...UE 7 29 bit 5ÑReceiver Overrun Error Flag bit ROE 7 29 bit 6ÑTransmit Data Register Empty bit TDE 7 29 bit 7ÑReceive Data Register Full bit RDF 7 30 SSR register 8 13 bit 1ÑTransmitter Empty bit TRNE 8 13 bit 2ÑReceive Data Register Full bit RDRF 8 14 bit 2ÑTransmit Data Register Empty bit TDRE 8 13 bit 3ÑIdle Line Flag bit IDLE 8 14 bit 4ÑOverrun Error Flag bit OR 8 14 bit 5ÑParity Error bit PE 8...

Page 422: ...O bit 10 9 TOIE 9 9 TPCR register 9 8 bits 0 20ÑPrescaler Counter Value bits PC0 PC20 9 9 bit 21 23Ñreserved bits 9 9 reserved bitsÑbits 21 23 9 9 TPLR register 9 7 bits 0 20ÑPrescaler Load Value bits PL0 PL20 9 7 bits 21 22ÑPrescaler Source bits PL0 PL20 9 7 bit 23Ñreserved bit 9 8 reserved bitÑbit 23 9 8 Trace buffer 10 21 Trace mode enabling 10 18 in OnCE module 10 15 Trace Mode Enable bit TME ...

Page 423: ...2 31 2 32 2 33 2 34 2 35 Wired OR Select bit WOMS 8 10 WL0ÐWL1 bits 7 14 WOMS bit 8 10 Word Length Control bits WL0ÐWL1 7 14 Word Select bits WDS0 WDS2 8 8 WR signal 2 10 write enable signal 2 10 X X data RAM 3 6 X Memory Address Bus XAB 1 13 X Memory Data Bus XDB 1 13 X Memory Expansion Bus 1 13 XAB 1 13 XDB 1 13 XTAL 2 8 XTAL Disable bit XTLD 4 18 XTLD bit 4 18 Y Y data RAM 3 7 Y Memory Address ...

Page 424: ...EMORY CONFIGURATION CORE CONFIGURATION GENERAL PURPOSE I O HOST INTERFACE HI08 ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE SCI TIMER MODULE ON CHIP EMULATION MODULE JTAG PORT C BSDL LISTING I INDEX D PROGRAMMING REFERENCE A BOOTSTRAP PROGRAM B EQUATES ...

Page 425: ...EMORY CONFIGURATION CORE CONFIGURATION GENERAL PURPOSE I O HOST INTERFACE HI08 ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE SCI TIMER MODULE ON CHIP EMULATION MODULE JTAG PORT C BSDL LISTING I INDEX D PROGRAMMING REFERENCE A BOOTSTRAP PROGRAM B EQUATES ...

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