14-22
DSP56305 User’s Manual
MOTOROLA
CYCLIC CODE CO-PROCESSOR
Operating Modes
the user to change CFSR configuration after each step. Every step is activated by setting
PREN, and is halted automatically after completing a single shift of the session by
clearing PREN and entering the Idle state. A single step session in the Step-by-step
Cipher mode takes two DSP clocks to complete, therefore for proper operation, a step
can be re-activated (PREN = 1) every two or more DSP clock cycles.
14.5.2
Parity Coding Modes
When OPM1 is set, the CCOP operates in one of the Parity Coding modes. In these
modes the CFSRs are configured as shown in Figure 14-3 CFSR Configuration in the
Parity Coding Modes
on page 14-6. The Parity Coding modes are used to calculate a
Cyclic Redundancy Code (CRC) syndrome for encoding or decoding. When in the Parity
Coding modes:
• The Feedback Tap register (CFBT) specifies the position of the taps between
adjacent bits of the CFSR connected to the feedback line.
• The Feedforward Tap register (CFFT) specifies the position of the taps of the
pre-multiplier polynomial.
• The Bit Select register (CBSR) specifies which bits from the CFSR are selected for
use by the Zero Detect function.
• The Mask register (CMSK) selects the bit in the CFSR which drives the feedback
line. In both Parity Coding modes, the bit driving the feedback line is always
selected by programming Mask Register A (CMSKA).
In the Parity Coding modes, the Mask tap register (i.e. CMSKA) should have only one bit
set, specifying the CFSR (CFSRA) bit by which the feedback is driven (i.e. the degree of
the generator polynomial). In the Parity Coding modes the bitwise majority function and
the output phase are disabled. The Zero Detect function is enabled (if HOZD, CCSR Bit
9, is set) and can affect the processing. Therefore, the relevant output data are the
contents of the CFSRs, and in some cases the counter values.
14.5.2.1
Parity Coding Mode Using One CFSR
When OPM[1:0] = 10 only the first CFSR (CFSRA) is enabled. In this mode, cyclic parity
codes using generator polynomials of up to 24 stages (maximum degree of 24) can be
generated.
14.5.2.2
Parity Coding Mode Using Two Concatenated CFSRs
When OPM[1:0] = 11 only two CFSRs (CFSRA and CFSRB) are enabled and
concatenated together to form one double-length CFSR. CFSRB and CFSRA are
positioned on the left and right sides respectively, while the LSB of CFSRB drives the
MSB of CFSRA. In this mode, cyclic parity codes using generator polynomials of up to 48
Summary of Contents for DSP56305
Page 34: ...xxxii DSP56305 User s Manual MOTOROLA ...
Page 40: ...xxxvi DSP56305 User s Manual MOTOROLA ...
Page 41: ...MOTOROLA DSP56305 User s Manual 1 1 SECTION 1 DSP56305 OVERVIEW ...
Page 58: ...1 18 DSP56305 User s Manual MOTOROLA DSP56305 Overview DSP56305 Architecture Overview ...
Page 59: ...MOTOROLA DSP56305 User s Manual 2 1 SECTION 2 SIGNAL CONNECTION DESCRIPTIONS ...
Page 98: ...2 40 DSP56305 User s Manual MOTOROLA Signal Connection Descriptions JTAG OnCE Interface ...
Page 99: ...MOTOROLA DSP56305 User s Manual 3 1 SECTION 3 MEMORY CONFIGURATION ...
Page 119: ...MOTOROLA DSP56305 User s Manual 4 1 SECTION 4 CORE CONFIGURATION ...
Page 144: ...4 26 DSP56305 User s Manual MOTOROLA Core Configuration JTAG Boundary Scan Register BSR ...
Page 145: ...MOTOROLA DSP56305 User s Manual 5 1 SECTION 5 GENERAL PURPOSE I O ...
Page 149: ...HOST INTERFACE HI32 MOTOROLA DSP56305 User s Manual 6 1 SECTION 6 HOST INTERFACE HI32 ...
Page 150: ...6 2 DSP56305 User s Manual MOTOROLA HOST INTERFACE HI32 ...
Page 259: ...MOTOROLA DSP56305 User s Manual 7 1 SECTION 7 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI ...
Page 315: ...MOTOROLA DSP56305 User s Manual 8 1 SECTION 8 SERIAL COMMUNICATION INTERFACE SCI ...
Page 347: ...MOTOROLA DSP56305 User s Manual 9 1 SECTION 9 TIMER EVENT COUNTER ...
Page 376: ...9 30 DSP56305 User s Manual MOTOROLA Timer Event Counter Timer Modes of Operation ...
Page 377: ...MOTOROLA DSP56305 User s Manual 10 1 SECTION 10 ON CHIP EMULATION MODULE ...
Page 411: ...MOTOROLA DSP56305 User s Manual 11 1 SECTION 11 JTAG PORT ...
Page 430: ...11 20 DSP56305 User s Manual MOTOROLA JTAG Port DSP56305 Boundary Scan Register ...
Page 431: ...Filter Co Processor MOTOROLA DSP56305 User s Manual 12 1 SECTION 12 FILTER CO PROCESSOR ...
Page 471: ...VITERBI CO PROCESSOR MOTOROLA DSP56305 User s Manual 13 1 SECTION 13 VITERBI CO PROCESSOR ...
Page 522: ...13 52 DSP56305 User s Manual MOTOROLA VITERBI CO PROCESSOR References ...
Page 554: ...14 32 DSP56305 User s Manual MOTOROLA CYCLIC CODE CO PROCESSOR Configuration Examples ...
Page 555: ...MOTOROLA DSP56305 User s Manual A 1 APPENDIX A BOOTSTRAP CODE ...
Page 568: ...A 14 DSP56305 User s Manual MOTOROLA Bootstrap Code ...
Page 569: ...Equates MOTOROLA DSP56305 User s Manual B 1 APPENDIX B EQUATES ...
Page 589: ...MOTOROLA DSP56305 User s Manual C 1 APPENDIX C JTAG BSDL ...
Page 590: ...C 2 DSP56305 User s Manual MOTOROLA JTAG BSDL ...
Page 600: ...C 12 DSP56305 User s Manual MOTOROLA JTAG BSDL ...
Page 601: ...MOTOROLA DSP56305 User s Manual D 1 APPENDIX D PROGRAMMING REFERENCE ...
Page 602: ...D 2 DSP56305 User s Manual MOTOROLA PROGRAMMING REFERENCE ...
Page 661: ...Y MOTOROLA DSP56305 User s Manual Index 11 ...
Page 662: ...Y Index 12 DSP56305 User s Manual MOTOROLA ...