6-80
DSP56305 User’s Manual
MOTOROLA
HOST INTERFACE (HI32)
HOST SIDE Programming Model
The CSTR/CCMR is a PCI standard 32-bit read/write register mapped into the PCI
configuration space, when in the PCI mode or in mode 0 (HM
=
$1 or $0). CSTR/CCMR is
accessed if a configuration read/write command is in progress and the PCI address is
$04. In the Self Configuration mode (HM = $5): the DSP56300 core can indirectly access
the CCMR. (see Section 6.7)
The CSTR/CCMR is written by the host in accordance with the byte enables. Byte lanes
that are not enabled are not written and the corresponding bits remain unchanged.
The CSTR/CCMR cannot be accessed by the host when not in the PCI mode (HM
≠
$1).
The CSTR/CCMR bits are described in the following paragraphs.
6.6.8.1
Memory Space Enable (MSE) Bit 1
The MSE bit is used to control the HI32 response to the PCI memory space accesses,
when in the PCI mode (HM
=
$1). The HI32 memory space response is disabled if MSE is
cleared and enabled if MSE is set.
The personal hardware reset clears MSE.
6.6.8.2
Bus Master Enable (BM) Bit 2
The BM bit is used to control the HI32 ability to act as a master on the PCI bus, when in
the PCI mode (HM
=
$1). If BM is cleared, the HI32 is disabled from acting as a bus
master. If BM is set, the HI32 can function as a bus master. This bit affects the MARQ bit
in the DSP side status register (DPSR): if BM is cleared, MARQ is also cleared.
The personal hardware reset clears BM.
6.6.8.3
Parity Error Response (PERR) Bit 6
The PERR bit is used to control the HI32 response to parity errors, when in the PCI mode
(HM
=
$1). If PERR is cleared: the HI32 does not drive HPERR. If PERR is set: if a parity
error is detected the HI32 pulses the HPERR signal. If a parity error or HPERR low is
detected, the HI32 sets the DPR bit in the CSTR/CCMR
In both cases the HI32 sets bit 15 (DPE) in the CSTR/CCMR, sets DPER in the DPSR, and
generates a parity error interrupt request if PEIE, in the DPCR, is set.
The personal hardware reset clears PERE.
6.6.8.4
Wait Cycle Control (WCC) Bit 7
The WCC bit is hardwired to zero, as the HI32 never executes address stepping.
Summary of Contents for DSP56305
Page 34: ...xxxii DSP56305 User s Manual MOTOROLA ...
Page 40: ...xxxvi DSP56305 User s Manual MOTOROLA ...
Page 41: ...MOTOROLA DSP56305 User s Manual 1 1 SECTION 1 DSP56305 OVERVIEW ...
Page 58: ...1 18 DSP56305 User s Manual MOTOROLA DSP56305 Overview DSP56305 Architecture Overview ...
Page 59: ...MOTOROLA DSP56305 User s Manual 2 1 SECTION 2 SIGNAL CONNECTION DESCRIPTIONS ...
Page 98: ...2 40 DSP56305 User s Manual MOTOROLA Signal Connection Descriptions JTAG OnCE Interface ...
Page 99: ...MOTOROLA DSP56305 User s Manual 3 1 SECTION 3 MEMORY CONFIGURATION ...
Page 119: ...MOTOROLA DSP56305 User s Manual 4 1 SECTION 4 CORE CONFIGURATION ...
Page 144: ...4 26 DSP56305 User s Manual MOTOROLA Core Configuration JTAG Boundary Scan Register BSR ...
Page 145: ...MOTOROLA DSP56305 User s Manual 5 1 SECTION 5 GENERAL PURPOSE I O ...
Page 149: ...HOST INTERFACE HI32 MOTOROLA DSP56305 User s Manual 6 1 SECTION 6 HOST INTERFACE HI32 ...
Page 150: ...6 2 DSP56305 User s Manual MOTOROLA HOST INTERFACE HI32 ...
Page 259: ...MOTOROLA DSP56305 User s Manual 7 1 SECTION 7 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI ...
Page 315: ...MOTOROLA DSP56305 User s Manual 8 1 SECTION 8 SERIAL COMMUNICATION INTERFACE SCI ...
Page 347: ...MOTOROLA DSP56305 User s Manual 9 1 SECTION 9 TIMER EVENT COUNTER ...
Page 376: ...9 30 DSP56305 User s Manual MOTOROLA Timer Event Counter Timer Modes of Operation ...
Page 377: ...MOTOROLA DSP56305 User s Manual 10 1 SECTION 10 ON CHIP EMULATION MODULE ...
Page 411: ...MOTOROLA DSP56305 User s Manual 11 1 SECTION 11 JTAG PORT ...
Page 430: ...11 20 DSP56305 User s Manual MOTOROLA JTAG Port DSP56305 Boundary Scan Register ...
Page 431: ...Filter Co Processor MOTOROLA DSP56305 User s Manual 12 1 SECTION 12 FILTER CO PROCESSOR ...
Page 471: ...VITERBI CO PROCESSOR MOTOROLA DSP56305 User s Manual 13 1 SECTION 13 VITERBI CO PROCESSOR ...
Page 522: ...13 52 DSP56305 User s Manual MOTOROLA VITERBI CO PROCESSOR References ...
Page 554: ...14 32 DSP56305 User s Manual MOTOROLA CYCLIC CODE CO PROCESSOR Configuration Examples ...
Page 555: ...MOTOROLA DSP56305 User s Manual A 1 APPENDIX A BOOTSTRAP CODE ...
Page 568: ...A 14 DSP56305 User s Manual MOTOROLA Bootstrap Code ...
Page 569: ...Equates MOTOROLA DSP56305 User s Manual B 1 APPENDIX B EQUATES ...
Page 589: ...MOTOROLA DSP56305 User s Manual C 1 APPENDIX C JTAG BSDL ...
Page 590: ...C 2 DSP56305 User s Manual MOTOROLA JTAG BSDL ...
Page 600: ...C 12 DSP56305 User s Manual MOTOROLA JTAG BSDL ...
Page 601: ...MOTOROLA DSP56305 User s Manual D 1 APPENDIX D PROGRAMMING REFERENCE ...
Page 602: ...D 2 DSP56305 User s Manual MOTOROLA PROGRAMMING REFERENCE ...
Page 661: ...Y MOTOROLA DSP56305 User s Manual Index 11 ...
Page 662: ...Y Index 12 DSP56305 User s Manual MOTOROLA ...