HOST INTERFACE (HI32)
DSP SIDE Programming Model
MOTOROLA
DSP56305 User’s Manual
6-43
6.5.6.13
Remaining Data Count (RDC5-RDC0) Bits 21-16
The read-only bits, RDC5-RDC0, indicate the PCI data phases remaining to complete a
PCI burst after the HI32 has completed a transaction as a PCI master. The RDC5-RDC0
bits are updated each time a transaction is terminated with the HI32 as a PCI master
(MARQ = 1).
If the transaction terminated normally, the value of RDC5-RDC0 will be $00 and TO = 0,
TRTY = 0, TDIS = 0, TAB = 0, MAB = 0.
If the master access counter was enabled and the burst was not completed for any reason
(typical examples being: the target initiated transaction termination or the HI32 was
required to generate a master initiated time-out transaction termination), the value of
RDC5-RDC0 will be the remaining number of data phases remaining to complete the
burst minus one (i.e. RDC = $2 signifies that there remain three more words to be
transferred to complete the burst). The length of the burst is limited by BL5-BL0 in the
DPMC.
6.5.6.14
DPSR Reserved Bits 23-22, 15-12 and 3
These bits are reserved for future expansion and are read as zeros.
6.5.7
Host To DSP Data Path
In PCI master data transfers (HM = $1) with FC
≠
$0, the host-to-DSP data path is a six
word deep, 24-bit wide FIFO. The host data is read into the host side of the FIFO (HTXR)
as 24-bit words, and the DSP56300 core reads 24-bit words from the DSP side (DRXR).
In PCI master data transfers (HM = $1) with FC = $0, and PCI target data transfers (HM
= $1) with HTF = $0, the host-to-DSP data path operates as a three word deep, 32-bit
wide FIFO. The host data is read into the HTXR as 32-bit words, and the DSP56300 core
reads from the DRXR 24-bit words. Each word read by the DSP56300 core contains
16-bits of data, right aligned and zero extended. The first word read by the DSP56300
core contains the two least significant bytes of the 32-bit word read into the HTXR. The
second word read by the DSP56300 core contains the two most significant bytes of the
32-bit word read into the HTXR.
In PCI target data transfers (HM = $1) with HTF
≠
$0 the host-to-DSP data path is a six
word deep, 24-bit wide FIFO. The host writes 24-bit words to the HTXR, and the
DSP56300 core reads 24-bit words from the DRXR.
In Universal Bus mode data transfers, the host-to-DSP data path is a five word deep,
24-bit wide FIFO. The host writes 24-bit words to the HTXR, and the DSP56300 core
reads 24-bit words from the DRXR.
The DSP side of the host-to-DSP data FIFO is described below. For a detailed description
of the host side see Section 6.2.2.
Summary of Contents for DSP56305
Page 34: ...xxxii DSP56305 User s Manual MOTOROLA ...
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Page 41: ...MOTOROLA DSP56305 User s Manual 1 1 SECTION 1 DSP56305 OVERVIEW ...
Page 58: ...1 18 DSP56305 User s Manual MOTOROLA DSP56305 Overview DSP56305 Architecture Overview ...
Page 59: ...MOTOROLA DSP56305 User s Manual 2 1 SECTION 2 SIGNAL CONNECTION DESCRIPTIONS ...
Page 98: ...2 40 DSP56305 User s Manual MOTOROLA Signal Connection Descriptions JTAG OnCE Interface ...
Page 99: ...MOTOROLA DSP56305 User s Manual 3 1 SECTION 3 MEMORY CONFIGURATION ...
Page 119: ...MOTOROLA DSP56305 User s Manual 4 1 SECTION 4 CORE CONFIGURATION ...
Page 144: ...4 26 DSP56305 User s Manual MOTOROLA Core Configuration JTAG Boundary Scan Register BSR ...
Page 145: ...MOTOROLA DSP56305 User s Manual 5 1 SECTION 5 GENERAL PURPOSE I O ...
Page 149: ...HOST INTERFACE HI32 MOTOROLA DSP56305 User s Manual 6 1 SECTION 6 HOST INTERFACE HI32 ...
Page 150: ...6 2 DSP56305 User s Manual MOTOROLA HOST INTERFACE HI32 ...
Page 259: ...MOTOROLA DSP56305 User s Manual 7 1 SECTION 7 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI ...
Page 315: ...MOTOROLA DSP56305 User s Manual 8 1 SECTION 8 SERIAL COMMUNICATION INTERFACE SCI ...
Page 347: ...MOTOROLA DSP56305 User s Manual 9 1 SECTION 9 TIMER EVENT COUNTER ...
Page 376: ...9 30 DSP56305 User s Manual MOTOROLA Timer Event Counter Timer Modes of Operation ...
Page 377: ...MOTOROLA DSP56305 User s Manual 10 1 SECTION 10 ON CHIP EMULATION MODULE ...
Page 411: ...MOTOROLA DSP56305 User s Manual 11 1 SECTION 11 JTAG PORT ...
Page 430: ...11 20 DSP56305 User s Manual MOTOROLA JTAG Port DSP56305 Boundary Scan Register ...
Page 431: ...Filter Co Processor MOTOROLA DSP56305 User s Manual 12 1 SECTION 12 FILTER CO PROCESSOR ...
Page 471: ...VITERBI CO PROCESSOR MOTOROLA DSP56305 User s Manual 13 1 SECTION 13 VITERBI CO PROCESSOR ...
Page 522: ...13 52 DSP56305 User s Manual MOTOROLA VITERBI CO PROCESSOR References ...
Page 554: ...14 32 DSP56305 User s Manual MOTOROLA CYCLIC CODE CO PROCESSOR Configuration Examples ...
Page 555: ...MOTOROLA DSP56305 User s Manual A 1 APPENDIX A BOOTSTRAP CODE ...
Page 568: ...A 14 DSP56305 User s Manual MOTOROLA Bootstrap Code ...
Page 569: ...Equates MOTOROLA DSP56305 User s Manual B 1 APPENDIX B EQUATES ...
Page 589: ...MOTOROLA DSP56305 User s Manual C 1 APPENDIX C JTAG BSDL ...
Page 590: ...C 2 DSP56305 User s Manual MOTOROLA JTAG BSDL ...
Page 600: ...C 12 DSP56305 User s Manual MOTOROLA JTAG BSDL ...
Page 601: ...MOTOROLA DSP56305 User s Manual D 1 APPENDIX D PROGRAMMING REFERENCE ...
Page 602: ...D 2 DSP56305 User s Manual MOTOROLA PROGRAMMING REFERENCE ...
Page 661: ...Y MOTOROLA DSP56305 User s Manual Index 11 ...
Page 662: ...Y Index 12 DSP56305 User s Manual MOTOROLA ...