MiTAC MiNote 7321, Service Manual

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7321 N/B Maintenance 7321 N/B Maintenance
5.3 VIA VT8231 BGA PCI-LPC/ISA South Bridge
Serial IRQ
Signal Name PIN # I/O Signal Description
SERIRQ V9 I Serial IRQ.
Chip Selects
Signal Name PIN # I/O Signal Description
ROMCS# /
KBCS#
T9 O / O ROM Chip Select (Rx5A[0]=1). Chip Select to the BIOS
ROM. See also Device 0 Rx40[5-4] and Rx41.
MCCS# /
GPO17/ strap
W6 O / IO Microcontroller Chip Select (Device 0 Function 4 RxE4[3]
= 0). Asserted during read or write accesses to I/O ports 62h
or 66h. Strap: 0/1 = Enable / Disable CPU Frequency
Strapping
PCS0#
/ GPO16 Y6 O / IO / IO
Programmable Chip Select 0.
(Device 0 Function 4 RxE4[2]
= 0). Asserted during I/O cycles to programmable read or
write ISA I/O port ranges.
PCS1# / GPI19/
GPO19
G5 O / I / O Programmable Chip Select 1. See Device 0 Func 4 RxE4[5]
and E5[1]
General Purpose Inputs
Signal Name PIN # I/O Signal Description
GPI0 F4 I / I General Purpose Input 0.
GPI1
V3 I / I
General Purpose Input 1.
GPI2 / EXTSMI# W1 I / IO General Purpose Input 2.
GPI3
/ RING# U3 I / I
General Purpose Input 3.
GPI4 / LID V2 I / I General Purpose Input 4.
GPI5
/ BATLOW# T3 I / I
General Purpose Input 5.
GPI6 / PME# U1 I / I General Purpose Input 6.
GPI7
/ SMBALRT# T2 I / I
General Purpose Input 7.
GPI8 / INTRUDER# F3 I / I General Purpose Input 8.
GPI9 / APICCLK Y3 I / I General Purpose Input 9. Rx58[6]=0
GPI10 / HREQ1# Y11 I / I General Purpose Input 10. F4 RxE5[3]=1
GPI11 / HREQ2# V11 I / I General Purpose Input 11. F4 RxE5[3]=1
GPI12 / LREQ1# U10 I / I General Purpose Input 12. F4 RxE5[2]=1
GPI13 / LREQ2# W10 I / I General Purpose Input 13. F4 RxE5[2]=1
GPI14
/ WSC# V4 I / I
General Purpose Input 14.
Rx58[6]=0
GPI15 / LDRQ# Y8 I / I / I General Purpose Input 15. Rx58[5]=0 & F4
RxE5[7]=0
GPI16 / CPUMISS V1 I / I General Purpose Input 16.
GPI17 / AOLGPI /
THRM
P3 I / I / I General Purpose Input 17. F4 Rx40[7]=1
GPI18 / GPO18 /
FAN2 / SLPBTN#
K3 I / O / I / I General Purpose Input 18. F4 RxE5[0]=0
GPI19 / GPO19
/
PCS1#
G5 I / O / I / O
General Purpose Input 19.
F4 RxE5[1]=0 &
E4[5]=1
GPI20 / GPO20 /
LA20 / USBOC2#
W13 I / O / IO / I General Purpose Input 20. F4 RxE4[6]=0, PMIO
4E[4]=1
GPI21 / GPO21 /
LA21 / USBOC3#
Y13 I / O / IO / I General Purpose Input 21. F4 RxE4[6]=0, PMIO
4E[5]=1
GPI22 / GPO22
/
IOR#
U7 I / O / IO
General Purpose Input 22.
F4 RxE4[7]=0, PMIO
4E[6]=1
GPI23 / GPO23 /
IOW#
T7 I / O / IO General Purpose Input 23. F4 RxE4[7]=0, PMIO
4E[7]=1
GPI24 / GPO24 /
GPIOA
Y2 I / O / IO General Purpose Input 24. F4 RxE6[0]=0
Internal Keyboard Controller
Signal Name PIN # I/O Signal Description
MSCK / IRQ1 N2 IO / I MultiFunction Pin (Internal mouse controller enabled by Rx5A[1])
Rx5A[1]=1 Mouse Clock. From internal mouse controller.
Rx5A[1]=0 Interrupt Request 1 . Interrupt 1 (external KBC).
MSDT / IRQ12 N4 IO / I MultiFunction Pin (Internal mouse controller enabled by Rx5A[1])
Rx5A[1]=1 Mouse Data. From internal mouse controller.
Rx5A[1]=0 Interrupt Request 12 . Interrupt 12 (ext PS2 mouse
ctlr).
KBCK /
A20GATE
M4 IO / I MultiFunction Pin (Internal keyboard controller enabled by
Rx5A[0])
Rx5A[0]=1
Keyboard Clock. From internal keyboard controller
Rx5A[0]=0 Gate A20. Input from external keyboard controller.
KBDT / KBRC N1 IO / I MultiFunction Pin (Internal keyboard controller enabled by
Rx5A[0])
Rx5A[0]=1
Keyboard Data. From internal keyboard controller.
Rx5A[0]=0 Keyboard Reset. From external keyboard controller
(KBC) for CPURST# generation
KBCS# /
ROMCS#
T9 O / O Keyboard Chip Select (Rx5A[0]=0). To external keyboard
controller chip.
5. Pin Descriptions of Major Components