MiTAC MiNote 7321, Service Manual

Page: 102 / 192

101
7321 N/B Maintenance 7321 N/B Maintenance
5.4 PC Card Interface controller
CardBus PC Card Address and Data (Slots A and B)
TERMINAL
NO.
SLOT A† SLOT B‡
NAME
PDV GHK PDV GHK
I/O DESCRIPTION
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0 147
145
144
142
141
133
132
131
128
126
125
123
121
119
118
103
101
102
99
100
98
97
95
93
92
89
90
87
88
84
85
83
F19
G17
G18
H15
H14
J19
K14
K15
K19
L15
L17
L19
M18
M15
N19
U15
V15
R14
W15
P14
U14
R13
W14
U13
V13
P12
R12
V12
U12
P11
R11
U11
81
79
78
77
76
67
66
65
62
60
59
57
55
54
53
37
35
36
33
34
32
30
29
27
26
23
24
20
21
18
19
17 W11
R10
U10
V10
W10
R8
W7
V7
W6
V6
U6
V5
R6
U5
W4
M6
M2
M3
L5
M1
L6
L2
L1
K5
K3
J6
K1
J2
J3
H1
J1
H2
I/O
CardBus address and data. These signals make
up the multiplexed CardBus address and data bus
on the CardBus interface. During the address
phase of a CardBus cycle, CAD31–CAD0
contain a 32-bit address. During the data phase of
a CardBus cycle, CAD31–CAD0 contain data.
CAD31 is the most significant bit.
TERMINAL
NO.
SLOT A† SLOT B‡
NAME
PDV GHK PDV GHK
I/O DESCRIPTION
CC/BE3
CC/BE2
CC/BE1
CC/BE0 130
117
104
94 K17
N18
W16
P13 63
52
39
28 P8
T1
N1
K6 I/O CardBus bus commands and byte enables.
CC/BE3–CC/BE0 are multiplexed on the same
CardBus terminals. During the address phase of a
CardBus cycle, CC/BE3–CC/BE0 define the bus
command. During the data phase, this 4-bit bus is
used as byte enables. The byte enables determine
which byte paths of the full 32-bit data bus carry
meaningful data. CC/BE0 applies to byte 0
(CAD7–CAD0), CC/BE1 applies to byte 1
(CAD15–CAD8), CC/BE2 applies to byte 2
(CAD23–CAD8), and CC/BE3 applies to byte 3
(CAD31–CAD24).
CPAR 106 R17 41 N3 I/O CardBus parity. In all CardBus read and write
cycles, the PCI1420 calculates even parity across
the CAD and CC/BE buses. As an initiator
during CardBus cycles, the PCI1420 outputs
CPAR with a one-CCLK delay. As a target
during CardBus cycles, the calculated parity is
compared to the initiator’s parity indicator; a
compare error results in a parity error assertion.
† Terminal name for slot A is preceded with A_. For example, the full name for terminals 106 and
R17
are A_CPAR.
‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 41 and N3
are B_CPAR.
5. Pin Descriptions of Major Components