MiTAC MiNote 7321, Service Manual

Page: 83 / 192

82
7321 N/B Maintenance 7321 N/B Maintenance
5.1 Mobile AMD K7 Processor
Detailed Ball Descriptions
Name Description
A20M# Ball A20M# is an input from the system used to simulate address wrap-around
in the 20-bit 8086.
AMD Athlon™
Processor System Bus
Balls See the AMD Athlon™ and AMD Duron™ Processor System Bus
Specification , order# 21902 for information about the system bus
balls —PROCRDY, PWROK, RESET#, SADDIN[14:2]#,
SADDINCLK#, SADDOUT[14:2]#, SADDOUTCLK#, SCHECK[7:0]#,
SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAINVALID#,
SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#.
Analog Ball Treat this ball as a NC.
CLKFWDRST Ball CLKFWDRST resets clock-forward circuitry for both the system and
processor.
CLKIN and RSTCLK
(SYSCLK) Balls Connect CLKIN (AC16) with RSTCLK (AC17) and name it SYSCLK.
Connect CLKIN# (AD16) with RSTCLK# (AD17) and name it
SYSCLK#. Length match the clocks from the clock generator to the
Northbridge and processor.
See “SYSCLK and SYSCLK#”, for more information.
CONNECT Ball
CONNECT is an input from the system used for power management and
clock-forward initialization at reset.
COREFB and
COREFB# Balls
COREFB and COREFB# are outputs to the system that provide processor
core voltage feedback to the system.
CPU_PRESENCE#
Ball CPU_PRESENCE# is connected to VSS on the processor package. If
pulled-up on the motherboard, CPU_PRESENCE# may be used to detect
the presence or absence of a processor.
DBRDY and DBREQ#
Balls DBRDY (AB2) and DBREQ# (T4) are routed to the debug connector.
DBREQ# is tied to VCC_CORE with a pullup resistor.
FERR Ball FERR is an output to the system that is asserted for any unmasked
numerical exception independent of the NE bit in CR0. FERR is an
open-drain active High signal that must be inverted and level shifted to an
active Low signal. For more information about FERR and FERR#, see
the “Required Circuits” chapter of the
AMD Athlon™ Processor
Motherboard Design Guide , order# 24363.
FID[3:0] Balls The FID[3:0] balls drive a value of: FID[3:0] = 0 1 0 0
that corresponds to a 5x SYSCLK multiplier after PWROK is asserted to
the processor. This information is used by the Northbridge to create the
SIP stream that the Northbridge sends to the processor after RESET# is
deasserted.
For more information, see “SYSCLK Multipliers”.
FLUSH# Ball
FLUSH# must be tied to VCC_CORE with a pullup resistor. If a debug
connector is implemented, FLUSH# is routed to the debug connector.
IGNNE# Ball IGNNE# is an input from the system that tells the processor to ignore
numeric errors.
Name Description
INIT# Ball INIT# is an input from the system that resets the integer registers without
affecting the floating-point registers or the internal caches. Execution
starts at 0FFFF FFF0h.
INTR Ball INTR is an input from the system that causes the processor to start an
interrupt acknowledge transaction that fetches the 8-bit interrupt vector
and starts execution at that location.
JTAG Balls TCK (V1), TMS (K3), TDI (W2), TRST# (Y1), and TDO (Y2) are the
JTAG interface. Connect these balls directly to the motherboard debug
connector. Pullup TDI, TCK, TMS, and TRST# to VCC_CORE with
pullup resistors.
K7CLKOUT and
K7CLKOUT# Balls K7CLKOUT (AC19) and K7CLKOUT# (AD19) are each run for 2 to 3
inches and then terminated with a resistor pair, 100 ohms to VCC_CORE
and 100 ohms to VSS. The effective termination resistance and voltage
are 50 ohms and VCC_CORE/2.
NC Balls The motherboard should provide a surface mount pad for all 564 package
balls. The pads for NC balls should not be electrically connected to
anything.
NMI Ball NMI is an input from the system that causes a non-maskable interrupt.
PLL Bypass and Test
Balls PLLTEST# (AA3), PLLBYPASS# (AB23), PLLMON1 (AD13),
PLLMON2 (AC13), PLLBYPASSCLK (AB17), and PLLBYPASSCLK#
(AB16) are the PLL bypass and test interface. This interface is tied
disabled on the motherboard. All six ball signals are routed to the debug
connector. All four processor inputs (PLLTEST#, PLLBYPASS#,
PLLMON1, and PLLMON2) are tied to VCC_CORE with pullup
resistors.
PWROK Ball The PWROK input to the processor must not be asserted until all voltage
planes in the system are within specification and all system clocks are
running within specification.
For more infor mation, s ee “Signal and Power -Up Requirements”.
RSVD Balls Reserved balls must have pulldown resistors to ground on the
motherboards.
SADDIN[1:0]# and
SADDOUT[1:0]# Balls The mobile AMD Athlon H-series OBGA processor model 6 does not
support SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to
VCC_CORE with pullup resistors, if this bit is not supported by the
Northbridge (future models of the AMD Athlon processors may support
SADDIN[1] #) . SADDOUT[1:0]# are tied to VCC_CORE with pullup
resistors if these balls are supported by the Northbridge. For more
information, see the
AMD Athlon™ and AMD Duron™ Processor
System Bus Specification , order# 21902.
5. Pin Descriptions of Major Components