7I43 20
SUPPLIED CONFIGURATIONS
USBIOPR8
GENERAL
The USBIOPR8 configuration is a simple six port GPIO configuration almost
identical to the EPPIOPR configuration. It is different because the USB interface is a
simple bidirectional byte-stream without separate address and data. Because of this a
Little Binary Protocol (LBP) is used to communicate with standard addressable peripherals
in the 7I43 FPGA configuration. The GPIO is organized as six eight bit ports, each with an
associated Data Direction Register (DDR).The USBIOPR8 configuration can be used as
a starting point for more complicated user configurations. There are two USBIOPR8
configuration files, USBIO8-2.BIT for the 200K and USBIO8-4.BIT for 400K versions of the
7I43.
PORT
DATA REG
DDR
IO BITS
CONNECTOR
0
0x010
0x020
0..7
P4
1
0x011
0x021
8..15
P4
2
0x012
0x022
16..23
P4
3
0x013
0x023
24..31
P3
4
0x014
0x024
32..39
P3
5
0x015
0x025
40..47
P3
In addition to the GPIO bits, the USBIOPR8 configuration has a simple SPI interface
to the configuration EEPROM, a LED port, and a reconfiguration port.. The SPI port allows
the utility program SCM7I43W to write configuration data to the serial EEPROM. These
registers are mapped as follows:
REGISTER ADDRESS
FUNCTION
LED
0x07A
8 Status LEDS (‘1' = on)
SPICS
0x07D
Single I/O bit to control SPI Chip Select (bit 0)
SPIDATA
0x07E
Eight bit SPI shift register
RECONFIG 0x07F
Reconfig - Writing 0x5A here resets FPGA
