7I43 10
OPERATION
FPGA
The 7I43/7I43H uses a Xilinx Spartan-III FPGA in a 144 pin QFP package, Either
PN XC3S200-5PQ144C or XC3S400-5PQ144C depending on 7I43 model.
HOST INTERFACE
The 7I43 uses either a USB or EPP printer port interface to the host. The 7I43H is
USB only. These interfaces can be used for programming the FPGA and accessing the
FPGA once programmed.
EPP CONFIGURATION
When the7I43 is jumpered so the configuration source is EPP, and the FPGA is not
configured (DONE is low), the on card CPLD implements two EPP registers to allow
configuring the FPGA via the EPP port.
The two EPP registers are the control register and the data register. The control
register is at EPP address 1 and has a single output bit (at D0) that controls FPGA
/PROGRAM, and a single input bit (at D0) that reads the FPGA’s done status. The data
register at EPP address 0, is used for the byte wide configuration data. Reads from the
data register will return the FPGA size in D0, 1 = 400K and 0 = 200K.
EPP CONFIGURATION PROCEDURE
EPPWriteAddress(1)
; Select EPP address 0x01 = control register
EPPWriteData(0)
; Set /PROGRAM low
EPPWriteData(1)
; Set /PROGRAM High
(Wait 100 Usec)
; Wait 100 Usec for FPGA to initialize
EPPWriteAddress(0)
; Select EPP address 0x00 = data register
EPPReadData
; Verify FPGA size
EPPWriteData(FPGAByte0)
; Write first byte of FPGA config data
EPPWriteData(FPGAByte1)
; Write second byte of FPGA config data
(write remaining FPGA config bytes)