7I43 3
HARDWARE CONFIGURATION
CONNECTOR POWER
The power connection on both I/O connectors (Pin 49) can supply either 3.3V or
5V power. Supplied power should be limited to 400 mA total. W1 selects the power
supplied to both P3 and P4 . When W1 is in the "UP" position, 5V power is supplied to the
connector. When W1 is in the "DOWN" position, 3.3V power is supplied to P3 and P4.
Note that most Mesa I/O adapter cards that connect to Anything I/O cards require 5V.
BUS SWITCH MODE
Jumper W2 determines bus switch mode for all user I/O pins. When jumper W2 is
in the "UP" position, 5V tolerant mode is selected, when ‘down’, 3.3V mode is selected.
Note that 3.3V mode is not 5V tolerant. The FPGA can be damaged by input voltages
greater than 4V in 3.3V mode.
PRE-CONFIGURATION PULL-UPS
The 7I43 has no pull-up resistors on its user I/O pins. This means that before these
pins are configured, they will not have a defined state. If this is not desired, internal pull-up
resistors on all FPGA pins can be enabled via Jumper W3. When W3 is in the "DOWN"
position, user I/O will float until the FPGA is configured. When W3 is in the "UP" position,
all FPGA pins including user I/O pins will have a pull-up resistor to 3.3V so the pins will be
in a "HIGH" state. It is suggested that the internal pull-ups be enabled unless this causes
a problem with connected I/O devices. Note that once the FPGA is configured, each FPGA
input pin can have programmable pull-up or pull-down resistors.
