7I43 12
OPERATION
EEPROM CONFIGURATION
For stand-alone applications and when it is not desired to have to preconfigure the
FPGA via the host interface at power up, the 7I43 can be configured via its serial
EEPROM. Of course the Serial EEPROM must first be programmed with the desired
configuration file. The serial EEPROM used is a ST M25P20 SPI flash serial EEPROM.
All access the serial EEPROM is via the FPGA, so programming the serial
EEPROM is a "bootstrap" process, where the first step is programming the FPGA with a
configuration giving host (EPP or USB) access to the serial EEPROM through the FPGA.
Both the EPP and USB GPIO demo configurations allow this EEPROM access via a
simple SPI interface built into the configuration.
The SCM7I43P program is an example program for writing the serial EEPROM via
the EPP port (DOS only), SCM7I43W is a similar example program for writing the serial
EEPROM via the USB port (windows only) The SCM programs rely on EPPIOPR8 (for
EPP programming or USBIOPR8 (for USB) configuration file being preloaded into the
FPGA before writing the serial EEPROM, as the serial EEPROM can only be accessed
through the FPGA. EPPIOPR8 and USBIOPR8 have a simple SPI interface to allow
EEPROM access.
EXTRA EEPROM SPACE
The serial configuration EEPROM on the 7I43 has a capacity of 256K bytes, but the
configuration bit file for the 400K Spartan 3 chip is only ~208K bytes, leaving 48 K bytes
free for FPGA accessible non volatile storage. The 200K gate Spartan 3 chip uses only
~128K bytes of the serial EEPROM leaving 128K bytes free. This storage can be used for
non-volatile settings or program storage in stand-alone 7I43 applications.
