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Summary of Contents for ACL-7122

Page 1: ...cess underutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of their respect...

Page 2: ...ACL 7122 144 Bit Parallel Digital I O Board User s Manual ...

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Page 4: ... the possibility of such damages This document contains proprietary information protected by copyright All rights are reserved No part of this manual may be reproduced by any mechanical electronic or other means in any form without prior written permission of the manufacturer Trademarks ACL 7122 is registered trademarks of ADLink Technology Inc Advantech and PCL 722 are trademark of Advantech Co L...

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Page 6: ...3 Chapter 2 Installation 5 2 1 What You Have 5 2 2 Unpacking 6 2 3 ACL 7122 s Layout 7 2 4 Jumper and DIP Switch Description 8 2 5 DIO Channel No Setting 8 2 6 Base Address Setting 9 2 7 Interrupt Setting 11 2 8 Connector Pin Assignment 14 2 9 Connection 16 Chapter 3 Digital I O Programming 17 3 1 Register Structure Format 17 ...

Page 7: ...ii Contents 3 2 Mode 0 of 8255 PPI 18 3 3 Interrupt Handling 19 3 4 Programming Notes 20 3 5 Programming in C language 22 Appendix A I O Port Address Map 25 Product Warranty Service 27 ...

Page 8: ...s an overview of the product features applications and specifications Chapter 2 Installation describes how to install the ACL 7122 The layout of ACL 7122 is shown the DIP switch setting for base address and jumpers setting for IRQ level and interrupt status are specified Chapter 3 Digital I O Programming describes how to program the digital input and output channels on the ACL 7122 Appendix A I O ...

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Page 10: ... Programmable Peripheral Interface PPI chips each offers 3 ports PA PB and PC PC is subdivided into 2 nibble wide 4 bit ports Each channel has an individual connector with OPTO 22 pin assignment It is very essential to use isolated input to prevent the ground loop problems The ACL 7122 is programmed using simple 8 bit I O port commands Users can use high level language such as BASIC C or PASCAL or...

Page 11: ...ts for higher driving Direct interface with OPTO 22 compatible I O module Programmable interrupt handling Output status readback Fully hardware and software compatible with Advantech PCL 7122 1 2 Applications High density programmable mixed digital input output Industrial monitoring and control Digital I O control Contact closure switch keyboard monitoring Connects with OPTO 22 compatible modules ...

Page 12: ...6 mA Logic Low Current 24 0 mA Output Signal Port C Logic High Voltage Minimum 2 4 V Logic Low Voltage Maximum 0 4V Logic High Current 15 0 mA Logic Low Current 24 0 mA Operating Temperature 0 60 C Storage Temperature 20 80 C Humidity 5 95 non condensing I O Connector 50 pin male ribbon cable connector Bus PC AT Bus I O port address Hex 200 Hex 3F8 Power Consumption 5V 1 4 A Typical 5V 1 8 A Maxim...

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Page 14: ... setting for the ACL 7122 s base address and interrupt IRQ level are also specified 2 1 What You Have In addition to this manual the package includes the following items ACL 7122 144 bit Parallel Digital I O Card If any of these items is missing or damaged contact the dealer from whom you purchased the product Save the shipping materials and carton in case you want to ship or store the product in ...

Page 15: ...age Shipping and handling may cause damage to your module Be sure there are no shipping and handing damages on the module before processing After opening the card module carton exact the system module and place it only on a grounded anti static surface component side up Again inspect the module for damage Press down on all the socketed IC s to make sure that they are properly seated Do this only w...

Page 16: ...Installation 7 2 3 ACL 7122 s Layout SW1 JP7 144 96 JP0 JP1 JP2 JP3 JP4 JP5 1514121110 9 7 6 5 4 3 JP6 Figure 2 1 ...

Page 17: ...the plastic cap inserted over two pins of the jumper A jumper is open with the plastic cap inserted over one or no pin s of the jumper 2 5 DIO Channel No Setting The ACL 7122 can provide two kinds of I O capability modes 144 bit and 96 bit which are selected by DIP switch JP7 see Figure 2 2 below The 144 bit mode requires 32 consecutive I O address ports and 96 bit mode just occupies 16 address po...

Page 18: ...ase address must be within the range 200hex to 3FFhex 2 The base address should not conflict with any PC reserved I O address refer to Appendix A The ACL 7122 requires 32 consecutive address locations for 144 bit mode or 16 address locations for 96 bit mode The I O port base address is selectable by a 5 position DIP switch SW1 refer to Figure 2 3 The address setting of 144 bit mode for I O port fr...

Page 19: ... 1 X default setting X Don t care ON 0 OFF 1 A2 A8 are corresponding to address lines of ISA bus A9 is always 1 OFF Table 2 2 144 bit mode Note In 144 bit mode the base address line A4 is not in functional status so do not care the position of A4 of SW1 I O port Address hex 2 A8 3 A7 4 A6 5 A5 6 A4 200 20F ON ON ON ON ON 290 29F ON OFF ON ON OFF 2A0 2AF ON OFF ON OFF ON 3D0 3DF OFF OFF OFF ON OFF ...

Page 20: ...u how to define the base address as Hex 2C0 Base Address Hex 2C0 2 C 0 1 0 1 1 0 0 0 0 0 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OFF ON OFF OFF ON ON 2 7 Interrupt Setting The ACL 7122 provides 11 interrupt requests IRQ 3 4 5 6 7 9 10 11 12 14 and 15 which could be set for hardware interrupt generated by pins PC 0 and PC 3 of each channel The IRQ is set by jumper JP6 Ref Figure 2 1 The IRQ signal is Tri s...

Page 21: ... event trapping is provided to determine which input was active first There are six jumpers JP0 to JP5 which are corresponding to each channel in ACL 7122 for interrupt enabled selection The figure 2 3 below shows three status of interrupt setting for CH3 JP3 D P E D P E D P E JP3 JP3 Default Setting D Disabled Interrupt No interrupt request P Programmable Interrupt interrupt when CH3 s PC4 is Low...

Page 22: ...E LOW L H L H HIGH LOW Interrupt Request JPn D P E HIGH X X LOW LOW No Interrupt Request JPn D P E X X HIGH No Interrupt Request JPn D P E HIGH X X LOW X Interrupt Request JPn D P E X X X Interrupt Request X Don t Care H L Rising Edge Trigger from High to Low L H Falling Edge Trigger from Low to High ...

Page 23: ...pose programmable peripheral interface Figure 2 4 shows ACL 7122 s equally block diagram There are six 50 pin connectors come equipped with the ACL 7122 board and each of them is corresponding to a mode 0 of 8255 The connector pin assignment is specified in Figure 2 5 below N 8255 CNN PC PA PB N N N N 0 5 Figure 2 4 ...

Page 24: ...ort C D4 Port C D3 Port C D2 Port C D1 Port C D0 Port B D7 Port B D6 Port B D5 Port B D4 Port B D3 Port B D2 Port B D1 Port B D0 Port A D7 Port A D6 Port A D5 Port A D4 Port A D3 Port A D2 Port A D1 Port A D0 5V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Figure 2 5 Connector Pin Assignment ...

Page 25: ...he TB 24R provides 24 Form C relays for digital output control The connection between ACL 7122 and TB 24R is ACL 7122 TB 24R 2 TB 24 P The TB 24P provides 24 opto isolated digital input channels the connection between ACL 7122 and TB 24R is ACL 7122 TB 24P 3 TB 16P8R The TB 16P8R provides 16 opto isolated digital input channels and 8 relay outputs the connection between ACL 7122 and TB 16P8R is AC...

Page 26: ... 2C1H EMULATE AS 8255 PB CH0 PC0 2C2H EMULATE AS 8255 PC CONTROL WORD CH0 2C3H EMULATE AS 8255 CW CH1 PA1 2C4H EMULATE AS 8255 PA CH1 PB1 2C5H EMULATE AS 8255 PB CH1 PC1 2C6H EMULATE AS 8255 PC CONTROL WORD CH1 2C7H EMULATE AS 8255 CW CH2 PA2 2C8H EMULATE AS 8255 PA CH2 PB2 2C9H EMULATE AS 8255 PB CH2 PC2 2CAH EMULATE AS 8255 PC CONTROL WORD CH2 2CBH EMULATE AS 8255 CW CH3 PA3 2CCH EMULATE AS 8255...

Page 27: ... 8 bit I O ports PA and PB wTwo nibble wide 4 bit ports PC upper and PC lower wAny ports can be used for both input and output wOutputs are latched whereas inputs are not latched w16 different input output configurations are available Two of the I O lines PC 0 PC 3 of each channel can be used to generate a hardware interrupt The I O of ACL 7122 emulates as six 8255 programmable peripheral interfac...

Page 28: ...nterrupt Handling The ACL 7122 can generate a hardware interrupt to your PC The following issues should be careful when you want to generate an interrupt trigger 1 Interrupt IRQ level setting make sure you already set the right IRQ level by using the jumper J6 Please refer to section 2 7 interrupt setting 2 Interrupt trigger status setting a interrupt mode make sure the jumper J2 is already set as...

Page 29: ...ed and no first event trapping is provided to determine which input was active first Self Interrupt Trigger Although the ACL 7122 s interrupt signals are normal received from external peripherals It can also generate a test output signal to emulate an interrupt being inputted from an external device An example program is shown in the section 3 5 for reference 3 4 Programming Notes Before programmi...

Page 30: ...E Data From Data Bus READ To Data Bus Figure 3 1 ACL 7122 s Signal Direction 3 According the above ACL 7122 s signal direction block diagram some issues should be careful a When a port is set as INPUT or after hardware RESET its output buffer is Disabled high impedance b The output data is lactated in the Output Latch when it is set as OUTPUT mode c When the port is set as OUTPUT the input circuit...

Page 31: ...efine BASE 0x2C0 define base address define CWD0 0x80 XX refer to 8255 CW int i for i 0 i 6 i outportb BASE i 4 0 0x00 outportb BASE i 4 1 0x00 outportb BASE i 4 2 0x00 outportb BASE i 4 3 CWD all as output 2 To write port define BASE 0x2C0 define base address define PA 0x0 Port A define PB 0x1 Port B define PC 0x2 Port C define CWD 0x80 ALL output to 8255 CW outportb BASE 3 CWD index to CH0 CW ou...

Page 32: ...me as SW setting define DATAS 0x301 data R W port define CW1 0x3 8255 port 0 CW index int dummy dummy data buffer outportb INDEX CW1 index to CW dummy inportb DATA dummy read to clear and enable interrupt 5 A Complete Example Program for Interrupt Handling This program deno how to generate interrupt by the ACL 7122 itself When you press any key a beep is generated When you press ESC key the system...

Page 33: ...sr getvect IRQ2 setvect IRQ2 isr_7122 mask inportb 0x21 outportb BASE_ADDR CW 0x80 set PA PB and PC as output mode clrscr clear screen printf press ESC to QUIT n do keyin 0 printf press any key to genetate an interrupt except ESC n keyin bioskey 0 outportb 0x21 0xbf mask IRQ2 nonmasked outportb BASE_ADDR PC 0x00 delay 100 outportb BASE_ADDR PC 0x08 while keyin 0xff 27 QUIT when ESC pressed setvect...

Page 34: ...er 0A0 0BF Interrupt controller 2 0C0 0DF DMA controller 0F0 0FF Math coprocessor 100 1EF not usable 1F0 1F8 Fixed disk 200 207 Game I O 278 27F Parallel printer port 2 LPT2 2F8 2FF Serial Port 2 COM2 300 31F Prototype card 360 36F Reserved 378 37F Parallel printer port 1 LPT1 3B0 3BF Monochrome display 3C0 3CF Reserved 3D0 3DF Color graphics display 3F0 3F7 Diskette controller 3F8 3FF Serial port...

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Page 36: ...g its specifications or if the serial number has been removed Seller does not assume any liability for consequential damages as a result from our products uses and in any event our liability shall not exceed the original selling price of the equipment The equipment warranty shall constitute the sole and exclusive remedy of any Buyer of Seller equipment and the sole and exclusive liability of the S...

Page 37: ...quipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentation Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate representative or authorized distributor for any manufacturer listed herein We re here to make your life easier How...

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