MeiG
Product
Manual
of
SLM750
Module
SLM750
Module
Hardware
Design
Page 55, total 84 pages
signal trace is 50 ohm (±10%).
Protect other sensitive signals/circuits (RF, analog signals, etc.) from SDIO corruption and
protect SDIO signals from noisy signals (clocks, DCDCs, etc.).
It is recommended to keep matching length between CLK and DATA/CMD less than 1mm and
total routing length less than 50mm.
Keep termination resistors within 15~24 ohm on clock lines near the module and keep the route
distance from the module clock pins to termination resistors less than 5mm.
3.17.2 BT Interface
SLM750 supports UART and PCM interface for BT application. Further information about BT
interface will be added in future version of this document.
3.18 SD Card Interface
SLM750 provides a SD card interface which supports SD 3.0 protocol. The following tables
show the pin definition.
Table 21: Pin Definition of the SD Card Interface
Pin name
Pin number
I/O Description
Note
SD_CMD
33
IO
SD card SDIO
bus instruction
signal
SDIO signal level can be selected
according to the signal level
supported by SD card. Please
refer to SD3.0 protocol for
details. suspend it when no used
SD_CLK
32
DO SD card SDIO
bus clock
signal
SDIO signal level can be selected
according to the signal level
supported by SD card. Please
refer to SD3.0 protocol for
details. suspend it when no used
SD_DATA3
28
IO
SD card SDIO
signal data line
3
SDIO signal level can be selected
according to the signal level
supported by SD card. Please
refer to SD3.0 protocol for
details. suspend it when no used
SD_DATA2
29
IO
SD card SDIO
signal data line
2
SDIO signal level can be selected
according to the signal level
supported by SD card. Please
refer to SD3.0 protocol for
details. suspend it when no used
