MeiG
Product
Manual
of
SLM750
Module
SLM750
Module
Hardware
Design
Page 53, total 84 pages
WLAN part
Pin name
Pin number I/O Description
Note
SDC1_DATA3
129
IO
WLAN SDIO signal
data line 3
1.8V power domain.
SDC1_DATA2
130
IO
WLAN SDIO signal
data line 2
1.8V power domain.
SDC1_DATA1
131
IO
WLAN SDIO signal
data line 1
1.8V power domain.
SDC1_DATA0
132
IO
WLAN SDIO signal
data line 0
1.8V power domain.
SDC1_CLK
133
DO WLAN SDIO signal
clock
1.8V power domain.
SDC1_CMD 134
IO
WLAN
SDIO
instruction signal
1.8V power domain.
WLAN_EN
136
DO WLAN enables
1.8V power domain.
Coexistence and control part
Pin name
Pin number I/O Description
Note
PM_ENABLE
127
DO External 3.3V power
control
1.8V power domain.
WLAN_SLP_CLK
118
DO WLAN sleep clock
Output 32kHz clock
WAKE_ON_WIREL
ESS*
135
DI
WLAN wakes up the
module
1.8V power domain,
pending development
COEX_UART_RX 137
DI
LTE/WLAN&BT
coexistence signal
1.8V power domain.
COEX_UART_TX 138
DO LTE/WLAN&BT
coexistence signal
1.8V power domain.
BT part
Pin name
Pin number I/O Description
Note
BT_EN 139
DO
Bluetooth
enables.
1.8V power domain.
Active high level.
BT_RTS*
37
DO Request sending data
1.8V power domain,
suspend it when unused
BT_TXD* 38
DO
Bluetooth
sends data
1.8V power domain.
BT_RXD* 39
DI
Bluetooth
receives
data
1.8V power domain.
BT_CTS* 40
DI
Bluetooth
sending
clearance
1.8V power domain.
PCM_IN 24
DI
PCM
data
input
1.8V power domain.
PCM_OUT
25
PCM data output
1.8V power domain.
PCM_CLK 27
IO
PCM
clock.
1.8V power domain.
PCM_SYNC 26
IO
PCM
data
synchronous
1.8V power domain.
