MeiG
Product
Manual
of
SLM750
Module
SLM750
Module
Hardware
Design
Page 51, total 84 pages
EPHY_INT_N 120
DI
Ethernet
PHY
interruption
1.8V /2.85V power domain.
SGMII_MDATA 121 IO
SGMII
MDIO
data
1.8V/2.85V power domain.
SGMII_MCLK 122
DO
SGMII
MDIO
clock
USIM2_VDD 128
PO
SGMII
MDIO
power supply
1.8V/2.85V power domain,
require external pull-up level for
SGMII SDIO Pin
SGMII_TX_M 123
AO
SGMII
data
transmit
negative signals
Connect with a 0.1uF capacitor,
close to the PHY side.
SGMII_TX_P 124
AO
SGMII
data
transmit
positive signals
Connect with a 0.1uF capacitor,
close to the PHY side.
SGMII_RX_P 125
AI
SGMII
data
receive positive
signals
Connect with a 0.1uF capacitor,
close to the PHY side.
SGMII_RX_M 126
AI
SGMII
data
receive
negative signals
Connect with a 0.1uF capacitor,
close to the PHY side.
The following figure shows the simplified block diagram for Ethernet application.
Figure 22 Simplified Block Diagram for Ethernet Application
The following figure shows a reference design of SGMII interface with PHY AR8033
application.
