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Maxim MAX3421E Programming Manual Download Page 46

 

46 

MAX3421E Programming Guide    

 

 

PWRDOWN 

 
Meaning:  

Power Down the MAX3421E. 

 
Mode: Peripheral 

and 

Host 

 

The CPU sets the PWRDOWN bit to put the chip into a low-power state, and clears the 
PWRDOWN bit to resume operation. 
 

Programming Notes

 

This bit is designed only for peripheral mode usage, although it is accessible in host mode. The 
CPU should never set POWERDOWN = 1 when operating as a host. 
 
 

 

 
 

Summary of Contents for MAX3421E

Page 1: ...rogramming Guide MISO Vcc GND D XI XO MOSI SCK SS INT RES GPX VBCOMP VL GND GPIN 7 0 GPOUT 7 0 D For more information on the MAX3421E please visit www maxim ic com max3421e For more information on USB...

Page 2: ...advantage of the new peripheral features read about the added registers R21 to R24 and the added bits PULSEWID1 0 SEPIRQ and HOST in this Programming Guide Then consult the MAX3420E Programming Guide...

Page 3: ...GPINIRQ6 GPINIRQ5 GPINIRQ4 GPINIRQ3 GPINIRQ2 GPINIRQ1 GPINIRQ0 RC R23 GPINIEN GPINIEN7 GPINIEN6 GPINIEN5 GPINIEN4 GPINIEN3 GPINIEN2 GPINIEN1 GPINIEN0 RSC R24 GPINPOL GPINPOL7 GPINPOL6 GPINPOL5 GPINPOL...

Page 4: ...IE RSC R15 USBCTL USBCTL HOSCSTEN VBGATE CHIPRES PWRDOWN CONNECT SIGRWU 0 0 RSC R16 CPUCTL CPUCTL PULSEWID1 PULSEWID0 0 0 0 0 0 IE RSC R17 PINCTL PINCTL EP3INAK EP2INAK EP1INAK FDUPSPI INTLEVEL POSINT...

Page 5: ...es the terms quite specifically and consistently SIE indicates that the MAX3421E sets or clears the bit CPU indicates that the SPI master attached to the MAX3421E sets or clears the bit Mode The MAX34...

Page 6: ...ister bits are asynchronously cleared However the register bits that are clocked from the SPI interface remain active so the CPU can control the SPI configuration e g the FDUPSPI bit USB bus pulldown...

Page 7: ...0 when HOST 1 EPSTALLS register CLRTOGS register EPIRQ register EPIEN register USBIRQ register except the VBUSIRQ and NOVBUS IRQ bits which remain active as a host USBIEN register except VBUSIRQ and N...

Page 8: ...terminates The MAX3421E has two register types FIFOS and control registers Repeated reads or writes to a register have different effects depending on the register type Registers R1 R2 and R4 access i...

Page 9: ...ks again at R31 MISO Values for the First Eight Bits in Full Duplex Mode When FDUPSPI 1 the MAX3421E operates its SPI port in full duplex mode meaning that data is simultaneously clocked in from the M...

Page 10: ...X3421E reports 16 host result conditions you will usually see one of the results shown in Table 3 Table 3 Host Result Codes for Normal USB Operation HSRLT Label Meaning 0x00 hrSUCCESS Successful Trans...

Page 11: ...eceiving ends agree that the data is accurate by generating receiving the ACK handshake they both complement their toggle values Therefore consecutive data packets sent to or received from an endpoint...

Page 12: ...lue 0010eeee Table 4 where eeee is the endpoint number to which it is sending the data The HXFR register is load sensitive which means that when the CPU loads the HXFR register the SIE initiates the t...

Page 13: ...oggle or assert the RCVDAVIRQ The SIE sets HRSL 0110 Toggle Error for this condition This situation would happen if the peripheral received a corrupted ACK handshake from the previous IN transfer In t...

Page 14: ...E sends fixed DATA0 and DATA1 PID tokens for the various stages of a CONTROL transfer regardless of the setting of the internal data toggle 2 Data optional If a data stage is required it is programmed...

Page 15: ...very frame This gives rise to special consideration for the MAX3421E which may be connected to a slow SPI interface or CPU The controller must keep pace with the scheduling requirements If there is a...

Page 16: ...thereby indicating that a FIFO is available for the CPU to load more data if necessary At the end of the ISO IN transfer EOP the SIE updates the HRSLT bits and asserts the HXFRDNIRQ Programming ISO OU...

Page 17: ...it loads HXFR register with 0110eeee As a FIFO becomes available the SIE continues to assert SNDBAVIRQ asking for the next chunk of ISO OUT data The double buffering allows the SIE to send OUT data fr...

Page 18: ...the IE Bit Table 2 shows the registers and bits that persist when the SPI master commands a MAX3421E mode change either from peripheral to host or from host to peripheral Therefore a mode change does...

Page 19: ...M 1 0 The CPU clears the BUSEVENTIRQ bit by writing a 1 to it The CPU sets and clears the BUSEVENTIE bit When BUSEVENTIE 1 the BUSEVENTIRQ is enabled as a source to activate the INT pin Programming No...

Page 20: ...ner causes the BUSEVENTIRQ to assert Programming Notes The CPU sets this bit to instruct the SIE to issue a bus reset on the D and D lines After setting this bit the CPU can detect the end of the 50ms...

Page 21: ...setting it Resetting the MAX3421E either at power on or by setting the CHIPRES bit clears most register bits including the HOST bit and therefore sets up the MAX3421E to operate as a USB peripheral de...

Page 22: ...ansition from 8 SE0 bit times to 25 microseconds of the J state or K state This indicates that a peripheral device has connected The CPU sets and clears the CONDETIE bit When CONDETIE 1 the CONDETIRQ...

Page 23: ...cket SOF timing conflict the DELAYISO bit determines whether the packet data or the SOF packet has priority If DELAYISO 1 the SIE checks the available time left in the 1 millisecond frame whenever the...

Page 24: ...er reads the remaining ISO IN data and does not generate the SOF packet or it delays sending the IN request until after it generates the next SOF packet Note Another ISO error condition is a data over...

Page 25: ...25 Note If ISO scheduling problems are detected the system must be modified to dispatch the ISO packets earlier in each frame perhaps by speeding up the SPI interface tuning the firmware or both...

Page 26: ...nects a 1500k resistor from D to 3 3V a full speed peripheral connects a 1500k resistor from D to 3 3V Because the bus is weakly pulled down the SIE can detect not only when a peripheral has plugged i...

Page 27: ...FDUPSPI 0 the MOSI Master Out Slave In pin becomes a bidirectional IO pin and the MISO Master In Slave Out pin is tri stated MOSI MISO 8 bit SR SPI Direction FDUPSPI 0 default Figure 3 Half duplex SP...

Page 28: ...in with the command remains in effect This ability to burst bytes is convenient when reading or writing the endpoint FIFOS For example to load 37 bytes into the EP0FIFO peripheral mode the SPI master...

Page 29: ...he SCK signal low for mode 0 0 and high for mode 1 1 In both modes the MOSI and MISO data sampled by the rising edge of SCK is the same Figure 6 SPI interface operating in mode 0 0 Figure 7 SPI interf...

Page 30: ...ver it generates a 1 millisecond frame marker that consists of a full speed SOF packet or a low speed keep alive pulse The CPU clears the FRAMEIRQ bit by writing a 1 to it The CPU sets and clears the...

Page 31: ...as meaning only when the MAX3421E is operating as a full speed host When operating as a low speed host there is no SOF packet or frame count After setting FRMRST 1 the next SOF packet will contain a f...

Page 32: ...edge GPINIRQ The MAX3421E sets a GPIN Interrupt Request bit when a signal on the GPIN pin makes a positive or negative transition The GPINPOL bit Table 5 controls the active edge polarity The GPINIRQ...

Page 33: ...ntrol the states of the GPOUT pins The output voltages are referenced to the voltage on the VL pin The CPU can also read these bits Reading the bit indicates the state of the output flip flop that dri...

Page 34: ...SACT or INIRQ 1 1 SOF 0 1 transition when SOF packet arrives 50 duty cycle signal If SEPIRQ 1 The default setting for the GPX output when GPXB 1 and GPXA 0 is BUSACT However if the SEPIRQ bit is set t...

Page 35: ...a RES pin reset the MAX3421E defaults to peripheral operation with the HOST bit set to 0 In this mode the MAX3421E operates as a MAX3420E peripheral only controller The CPU sets HOST 1 to operate the...

Page 36: ...e in HXFR reg 0x03 hrUNDEF reserved 0x04 hrNAK Peripheral returned NAK 0x05 hrSTALL Perpheral returned STALL 0x06 hrTOGERR Toggle error ISO over underrun 0x07 hrWRONGPID Received the wrong PID 0x08 hr...

Page 37: ...lears this bit Programming Notes If the host firmware detects during enumeration that it is talking to a low speed peripheral through a USB hub it sets HUBPRE 1 This instructs the SIE to precede every...

Page 38: ...es Table 7 HXFR Register Bit Settings for Different Transfer Types Xfr Type HS ISO OUTNIN SETUP hex SETUP 0 0 0 1 10 BULK IN 0 0 0 0 0 ep BULK OUT 0 0 1 0 2 ep HS IN 1 0 0 0 8 ep HS OUT 1 0 1 0 A ep I...

Page 39: ...bit when it has completed a host transfer The CPU clears the HXFRDNIRQ by writing a 1 to it The CPU sets and clears the HXFRDNIE bit When HXFRDNIE 1 the HXFRDNIRQ is enabled as a source to activate t...

Page 40: ...are determined by the INTLEVEL POSINT and PULSEWID 1 0 bits page 41 The CPU clears this bit to disable the INT output pin Programming Notes When IE 0 the state of the INT pin is inactive open for lev...

Page 41: ...rs the INTLEVEL bit to make the INT pin edge active When INTLEVEL 0 the edge polarity is set by the POSINT bit In edge output mode the INT pin driver is push pull so no pullup resistor to VL is requir...

Page 42: ...elivers an edge whenever a new interrupt request occurs or an interrupt request bit is cleared while others are pending If an interrupt is pending when another is cleared in edge mode the INT pin mome...

Page 43: ...e operation as a low speed USB host The CPU will normally set this bit when it discovers that a peripheral has plugged in activating CONDETIRQ and that the quiescent bus state is D 0 D 1 This bus cond...

Page 44: ...operate The SIE sets the OSCOKIRQ bit when the OSCOK signal makes a 0 1 transition indicating that the chip is ready to operate The CPU clears the OSCOKIRQ bit by writing a 1 to it The CPU sets and cl...

Page 45: ...SIE sends a token packet after the CPU loads the HXFR register it takes the peripheral address from this register If the CPU talks only to one device address the SIE can initialize this register once...

Page 46: ...Host The CPU sets the PWRDOWN bit to put the chip into a low power state and clears the PWRDOWN bit to resume operation Programming Notes This bit is designed only for peripheral mode usage although i...

Page 47: ...ng a data packet from the bus into the RCVFIFO the SIE updates this register with the received byte count and asserts the INDAVIRQ bit After the CPU has read the number of bytes indicated in the RCVBC...

Page 48: ...ds the byte count in the RCVBC register and does successive reads to the RCVFIFO register R1 to retrieve the data The SIE handles all retries due to PID CRC data toggle or timeout errors and only inte...

Page 49: ...AVIRQ bit Receive Data Available IRQ The CPU responds first by reading the RCVBC register to determine the number of bytes in the RCVFIFO clearing the RCVDAVIRQ bit and finally reading the bytes with...

Page 50: ...REVISION Register Meaning MAX3421E Revision Number Mode Peripheral and Host This read only register indicates the chip revision code Consult the Maxim website for current revision information Writing...

Page 51: ...ng a 1 to it The CPU sets and clears the RWUIE bit When RWUIE 1 the RWUIRQ is enabled as a source to activate the INT pin Programming Notes After the CPU suspends bus signaling by setting SOFKAEN 0 a...

Page 52: ...r two conditions 1 The CPU sets SAMPLEBUS 1 2 The CONDETIRQ asserts The second case indicates either a device attach or detach condition The CPU should respond to the CONDETIRQ by reading the JSTATUS...

Page 53: ...n SEPIRQ 0 IRQ Logic Generates Pulse or Level Output 2 USB IRQS GPX pin INTLEVEL POSINT GPIN IRQS BUSACT GPXB 1 GPXA 0 INT pin IRQ Logic Generates Pulse or Level Output 2 USB IRQS INTLEVEL POSINT GPIN...

Page 54: ...signal with a signal indicating any of the eight GPIN interrupts The dotted line in the bottom figure indicates that when the GPX pin functions as this second interrupt pin its characteristics as dete...

Page 55: ...rom automatically generating full speed SOF packets or low speed keep alive pulses every millisecond To resume bus activity the host sends a Resume signal consisting of a 20 millisecond K state follow...

Page 56: ...DBAVIRQ is enabled as a source to activate the INT pin Programming Notes The SIE clears its FIFO pointers at the termination of any host transfer Therefore if the host reads a nonzero HRSLT after an I...

Page 57: ...OUT data over the bus Programming Notes When the CPU loads the SNDBC register the SIE clears the SNDBAVIRQ bit If the second FIFO is available the SIE immediately re asserts the SNDBAVIRQ bit Unlike t...

Page 58: ...loaded When the CPU writes the byte count register the SIE negates the SNDBAVIRQ Send Buffer Available IRQ and commits the FIFO to USB transmission The SNDFIFO register connects to two internal 64 by...

Page 59: ...by using these bits After transferring data to the endpoint the CPU reads the toggle value in the SNDTOGRD or RCVTOGRD bit page 36 and stores this value in CPU local storage For multiple endpoints th...

Page 60: ...frame marker the SIE completes the signaling before shutting off the frame markers SOF Packets Every millisecond the SIE sends the SOF PID the contents of an internal 11 bit frame counter and a CRC5 v...

Page 61: ...O register eight times to load an internal 8 byte FIFO with data to be included in a SETUP packet Programming Notes The SUDFIFO has no associated byte count register because the payload is always eigh...

Page 62: ...Mode Host only The SIE asserts the SUSDNIRQ bit to indicate 3 milliseconds of bus activity This usually occurs 3 milliseconds after the SPU sets SOFKAENAB 0 The CPU clears the SISDNIRQ bit by writing...

Page 63: ...with separate interrupts for each edge 0 1 VBUSIRQ or 1 0 NOVBUSIRQ The VBCOMP pin has a weak 100k pulldown resistor to ground so no termination resistor is required when using the VBCOMP pin as a gen...

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