20
MAX3421E Programming Guide
BUSRST
Meaning:
Issue a Bus Reset to a USB peripheral.
Mode:
Host only
The CPU sets this bit to initiate a 50ms bus reset (SE0) signal to the peripheral.
The SIE clears this bit at the conclusion of the bus reset signaling.
The CPU may also clear this bit to prematurely terminate the 50ms SE0 bus signal. Terminating
the reset signal in this manner causes the BUSEVENTIRQ to assert.
Programming Notes
The CPU sets this bit to instruct the SIE to issue a bus reset on the D+ and D- lines. After setting
this bit, the CPU can detect the end of the 50ms interval either by polling the BUSRST bit for
zero, or by responding to the BUSEVENTIRQ. To program a bus reset, follow this sequence of
steps:
1. Set BUSRST = 1.
2. Test for BUSRST = 0 or respond to the BUSEVENTIRQ.
3. Turn on frame markers by setting SOFKAENAB = 1.
4. Wait for at least one FRAMEIRQ.
Step 4 ensures that the host logic is ready to generate the first host transaction.