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MAX3421E Programming Guide
Active Bits in Peripheral and Host Modes
Some MAX3421E features are available for both peripheral and host operation. These features
involve non-USB system aspects such as how the SPI master is configured, how the interrupt pin
operates, and the state of the IO pins. These features can be grouped as follows:
•
Interface Configuration
o
FDUPSPI
o
GPX[B:A]
o
INTLEVEL
o
POSINT
•
IO Pin configuration and Output Values
o
GPIN pins—interrupt polarity and enables
o
GPOUT pin states
o
VBCOMP pin detected level
•
Global Chip Operations
o
CHIPRES
o
PWRDOWN
o
OSCOK (Oscillator OK)
•
Some IRQ Bits and the IE Bit
shows the registers and bits that persist when the SPI master commands a MAX3421E
mode change, either from peripheral to host or from host to peripheral. Therefore, a mode change
does not disturb the SPI interface configuration or the GPOUT pin values. The IE bit and the
GPIN interrupt bits (GPINIRQ and GPINIE) remain unchanged through a mode change. This
means that if a GPIN interrupt is pending before the mode change, it will be pending after the
mode change.
Note:
There are two ways to command the MAX3421E to switch from HOST to PERIPHERAL
operation. First, the SPI master can write a zero to the HOST bit in the MODE register R27.
Second, the SPI master can set, then clear the CHIPRES bit in the USBCTL register R16. Using
CHIPRES is the preferred way if you want to start with a “clean” peripheral.