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FDUPSPI
Meaning:
Full-Duplex SPI port operation
Mode: Peripheral
and
Host
The CPU sets this bit to operate the SPI port in full-duplex mode.
The CPU clears this bit to operate in half-duplex mode.
POR:
FDUPSPI = 0 (half-duplex)
Chip Reset:
No change
Bus Reset:
No change
Pwr Down:
Read-write
Programming Notes
Half-duplex SPI
In half-duplex mode (FDUPSPI = 0), the MOSI (Master Out, Slave In) pin
becomes a bidirectional IO pin, and the MISO (Master In, Slave Out) pin is tri-stated.
MOSI
MISO
8-bit SR
SPI Direction
FDUPSPI=0 (default)
Figure 3. Half-duplex SPI interface.
Full-Duplex SPI
Full-duplex mode (FDUPSPI = 1) provides separate MOSI and MISO pins. This configuration
has the added feature that while the first byte of every transfer (the command byte) is clocked in,
eight bits of status information are simultaneously clocked out.
MOSI
MISO
8-bit SR
FDUPSPI=1
Figure 4. Full-duplex SPI interface.