Maxim Dallas Semiconductor DS3171, General Description Manual, Page: 54 / 234

DS3171/DS3172/DS3173/DS3174
54
10.2.1.2.4 LIU Disabled - CLAD Timing Enabled – no LB
In this mode, the RLCLKn pins source the clock for the receive logic and one of the CLAD clocks sources the clock
for the transmit logic.
10.2.2 Sources of Clock Output Pin Signals
The clock output pins can be sourced from many clock sources. The clock sources are the transmit input clocks
pins (TCLKIn), the receive clock input pins (RLCLKn), the recovered clock in the receive LIUs, and the clock
signals in the clock rate adapter circuit (CLAD). The default clock source for the receive logic is the RLCLKn pin if
the LIU is disabled; otherwise the default clock is sourced from the RX LIU clock when the RX LIU is enabled. The
default clock source for the transmit logic is the CLAD clocks.
The LIU is enabled based on the line mode bits(LM[2:0]) (See Table 10-26 ). The bits LM[2:0], LBM[2:0], LOOPT
and CLADC are located in the port configuration registers. LIUEN is not a register bit; it is a variable based on the
line mode bits.
Table 10-1 decodes the LM bits for LiUEN selection.
Table 10-1. LIU Enable Table
LM[2:0] LIUEN LIU Status
000 0 Disabled
001 1 Enabled
010 1 Enabled
011 1 Enabled
1XX 0 Disabled
Table 10-2 identifies the framer clock source and the line clock source depending on the mode that the device is
configured. Putting the device in loopback will typically mux in a different clock than the normal clock source.
Table 10-2. All Possible Clock Sources Based on Mode and Loopback
MODE LOOPBACK
Rx FRAMER
CLOCK
SOURCE
Tx FRAMER
CLOCK
SOURCE
Tx LINE
CLOCK
SOURCE
Loop Timed Any
RLCLKn or
RXLIU
Same as Rx Same as Rx
Normal None
RLCLKn or
RXLIU
TCLKIn or
CLAD
Same as Tx
Normal LLB
RLCLKn or
RXLIU
TCLKIn or
CLAD
Same as Rx
Normal PLB
RLCLKn or
RXLIU
Same as Rx Same as Rx
Normal DLB Same as Tx
TCLKIn or
CLAD
Same as Tx
Normal LLB and DLB Same as Tx
TCLKIn or
CLAD
RLCLKn or
RXLIUn
Table 10-3 identifies the source of the output signal TLCLKn based on certain variables and register bits.