Maxim Dallas Semiconductor DS3171, General Description Manual, Page: 38 / 234

DS3171/DS3172/DS3173/DS3174
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Figure 8-4. RX Line IO HDB3 Functional Timing Diagram
RLCLK
RPOS
RNEG
(RX DATA)
HDB3 CODEWORD
(RX LINE)
+
-
RXP
RXN
V
V
B
B
B V
B V
0 V
BIAS V
8.3.1.3 UNI Mode Transmit Pin Functional Timing
The TDATn pin is available when the line interface is in the UNI mode and the transmit line pins are enabled
The TDATn signal changes a small delay after the positive edge of the reference clock signal if the clock pin is not
inverted, other wise they change after the negative edge. The TLCLKn clock pin is the clock reference typically
used for the TDATn signal, but the TDATn can be time referenced to the TCLKIn, TCLKOn, RLCLKn or RCLKOn
clock pins. The TDATn pins can be inverted. See
Figure 8-5 .
Figure 8-5. TX Line IO UNI Functional Timing Diagram
8.3.1.4 UNI Mode Receive Pin Functional Timing
The RDATn pin is available when the line interface is in the UNI mode. The RLCVn pin is available when the line
interface is in the UNI
All bits on the RDATn pin, will come out the RSERn pin, if the RSERn pin is enabled.
The signal on the RLCVn pin enables the BPV counter, which is in the line interface, to increment each clock it is
high.
The RDATn and RLCVn signals are sampled at the rising edge of the reference clock signal if the clock pin is not
inverted; otherwise they are sampled at the negative edge. The RLCLKn clock pin is the clock reference used for
the RDATn and RLCVn signals. The RDATn and RLCVn pins can be inverted. See
Figure 8-6 .
TLCLK
TDAT