DS3171/DS3172/DS3173/DS3174
14
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FEAC port for DS3 FEAC channel can be configured to send one codeword, one codeword continuously, or
two different codewords back-to-back to send DS3 Line Loopback commands
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16-byte Trail Trace Buffer port for the G.832 trail access point identifier
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Insertion of G.832 payload type, and timing marker bits from registers
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DS3 M23 C bits configurable as payload or overhead, as overhead they can be controlled from registers or the
transmit overhead port
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Most framing overhead fields can be sourced from transmit overhead port
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Formatter bypass mode for clear channel or externally defined format applications
3.5 Transmit DS3/E3 LIU Features
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Wide 50+20% transmit clock duty cycle
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Line Build-Out (LBO) control
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Tri-state line driver outputs support protection switching applications
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Per-channel power-down control
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Output driver monitor status indication
3.6 Jitter Attenuator Features
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Fully integrated and requiring no external components
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Can be placed in transmit or receive path
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FIFO depth of 16 bits
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Standard compliant transmission jitter and wander
3.7 Clock Rate Adapter Features
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Generation of the internally needed DS3 (44.736 MHz) and E3 (34.368 MHz) clocks a from single input
reference clock
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Input reference clock can be 51.84 MHz, 44.736MHz or 34.368 MHz
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Internally derived clocks can be used as references for LIU and jitter attenuator
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Derived clocks can be transmitted off-chip for external system use
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Standards compliant jitter and wander requirements.
3.8 HDLC Overhead Controller Features
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Each port has a dedicated HDLC controller for DS3/E3 framer link management
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256-byte receive and transmit FIFOs
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Handles all of the normal Layer 2 tasks including zero stuffing/de-stuffing, FCS generation/checking, abort
generation/checking, flag generation/detection, and byte alignment
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Programmable high and low water marks for the transmit and receive FIFOs
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Terminates the Path Maintenance Data Link in DS3 C-bit Parity mode and optionally the G.751 Sn bit or the
G.832 NR or GC channels
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RX data is forced to all ones during LOS, LOF and AIS detection to eliminate false packets
3.9 FEAC Controller Features
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Each port has a dedicated FEAC controller for DS3/E3 link management
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Designed to handle multiple FEAC codewords without Host intervention
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Receive FEAC automatically validates incoming codewords and stores them in a 4-byte FIFO
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Transmit FEAC can be configured to send one codeword, one codeword continuously, or two different
codewords back-to-back to send DS3 Line Loopback commands
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Terminates the FEAC channel in DS3 C-Bit Parity mode and optionally the Sn bit in E3 mode