Operating and Technical Descriptions
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7.8.
Flicker Suppressor
The flicker suppressor is a digital field store, used to eliminate flicker
between alternate fields in 'chop' mode. Adjustments are provided for
clock frequency (RV209), RAM input-output data phase (RV210) [not
required on SMT version], alternate -line interlace (RV212) and store
vertical position (RV211). No adjustment of these should be necessary
during setting -up. The balance control RV208 may be used to minimise
flicker in the 'chop' mode.
7.9.
Output Video Level Clamp
Because the video signal is proportional to rate of change of
temperature and decays within a few seconds, unwanted changes in
black level can occur if the camera is moved after the signal from
objects in the field of view has decayed. In order to maintain a suitable
black level, an automatic circuit detects the coldest signal in the scene
and maintains its level 300mV above blanking level, in order that
details in cold objects can be seen.
8.
CIRCUIT DESCRIPTION
8.1.
The Synchronising Generator (Video Board)
The sync generator uses a RCA integrated circuit type CD22402,
which is locked to its own 500kHz crystal oscillator. Conversion from
625 lines 50Hz to 525 lines 60Hz is possible by opening the solder link
between pin 18 and 19 of the integrated circuit.
8.2.
Video Head Amplifier
The head amplifier is located on the video board and is a high gain, low
noise amplifier with a nominal bandwidth of 5MHz (6dB). The cascade
input stage utilises a J309 FET which has a low input capacitance and
a high Yfs. The LM733 [NE592] amplifier compensates for the falling
input frequency response by incorporating a capacitor which bypasses
its feedback loop. The output is then passed to the main video
amplifier.
8.3.
Video (ion Pedestal Stabilisation)
The video signal is clamped by Q210 [TR3] and then taken via P200/18
to the scan board where the unwanted positive pedestal portion of the
waveform is removed. The remaining negative pedestal is compared
with the reference voltage on RV110 (the pedestal drive control) and
the resultant output defines the voltage to which the G1 grid is switched
during the line flyback period. Hence the ion pedestal is maintained
against changes in the tube characteristics.
