Operating and Technical Descriptions
- 11 -
The store is arranged as 128 x 256 bytes of 6 bits each. This
corresponds to an array of 128 picture elements in each of 256 of the
288 lines in each field. This array is placed centrally on the screen by
delaying in both line and field directions. The field delay monostable
(1/2 V215)[IC14] is triggered by the trailing edge of field blanking,
generating a 'high' at its Q output which resets the line counter V218
[IC17]. The reset pulse disappears when Q returns to its low state after
a timing period of about 16 lines, and when the next line blanking edge
sets the line delay monostable (1/2 V215) [IC14], V218 [IC17] is
clocked and advances one count. The cycle repeats for 256 lines,
when the 9th bit of the line counter goes high, clearing the line delay
monostable and preventing further clock pulses. The line counter
remains in this State until the next field blanking edge, which resets the
line counter and enables the time delay monostable.
The pixel counter V216, V217 [IC15,16] is similar in operation. The
trailing edge of line blanking starts the line delay monostable whose Q
output clears the pixel counters. This clears the carry outputs and
enables the clock. Counting starts on the first clock pulse after the line
delay timer takes the clear inputs high, and progresses until the 127th
count, when the carry outputs of the pixel counter are both high. This
stops the clock via D218 and (1/4 V214) [D14 & IC13]and the counters
wait in this state until cleared by the next line blanking edge.
The 13 least significant addresses are used to address the RAMS
V221 -V224 [IC18]. The two most significant addresses are decoded in
(1/2 V219) to select one of the four RAMs at a time [simply addressed
SMT]. The other (1/2 V219) [IC 19 logic] is used as a divider to
generate alternate write and output enables from successive clock
cycles, after shaping by (1/4 V214) [IC13]. The write enable is also
used to enable the outputs of the A to D converter, (whose data
conversion is clocked from the master clock) so that data is available
for the RAM write cycle. On the previous clock cycle, the RAM outputs
are enabled to transfer data to the output latch V225 [IC20]where it is
held and converted to analogue form. This is then added to the direct
signal, which is delayed by 250ns to balance the RAM reading time
and propagation delays, in the summing amplifier V212 [TR20, TR21].
Storage effects on the circular blanking edge are removed by Q214
[TR16]and syncs are added by Q215 and Q216 [TR18, TR19]. Video
is distributed to the internal monitor and external video socket.
8.7.
Output Video Level Clamp (Video Board)
This circuit detects the most negative level appearing in picture period
(Q217, gated by D212) [TR17, D8], compares this level in V213 [IC10]
with a fixed reference set by R307 and R308 [R68,70], and applies an
error signal to V212 [TR20, TR21] via R293 [R65], maintaining the
most negative video excursion at a level suitable for observation.
