Lexicon CORE2, Service Manual

Page: 43 / 86

Lexicon
6-7
System Status Register
Register Bit
Number
Signal
Name
Function Active State
7 - not used -
6 - not used -
5 - not used -
4 - not used -
3 ADSAT4 DBX type 4 compression is active on channels 7&8 High
2 ADSAT3 DBX type 4 compression is active on channels 5&6 High
1 ADSAT2 DBX type 4 compression is active on channels 3&4 High
0 ADSAT1 DBX type 4 compression is active on channels 1&2 High
SPDIF TX Channel Status byte 3
Register Bit
Number
Function Active State
7 not used -
6 not used -
5 not used -
4 not used -
3 Encoded sampling frequency bit 3 see table below
2 Encoded sampling frequency bit 2 see table below
Encoded sampling frequency bit 1 see table below
0 Encoded sampling frequency bit 0 see table below
SPDIF sample rate encoding
Hex value Encoded Sample Rate
4 -15 Not used
3 32 KHz
2 48 KHz
1 Not used
0 44.1 KHz
Sample Clock Phase-Locked Loop (schematic sheet 3.)
The TLC2932 PLL I.C. (U30) is used to create a 256FS sample clock that is synchronized with an audio
word clock that may be derived from a number of sources. These sources are multiplexed in the FPGA and
sent to the PLL as the SAMP_REF signal. The INT_REF signal is the VCO256 signal divided by 256. The
PLL loop filter is comprised of R157, R159, C142, and C144. The 78L05 (U29) voltage regulator is used to
provide a stable 5V supply for the TLC2932 PLL. U22 is used as a clock driver, and U21 is a QS3245
powered through a diode which is used to limit the signals with “LV” suffixes to 3.3V logic levels.
PCI & Option Connectors (schematic sheet 4.)
All of the signals of the PCI interface (P1) are connected only to the DSP56301 with the exception of power
and ground pins . The Option connector (J2) is used to attach an MP-100 daughterboard. The Once port
emulator connector (J3) is only used for development.