Lexicon CORE2, Service Manual

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Lexicon
6-3
Startup Sequence
At power-up the DSP56301 (U23, sheet 1) is held in the reset state by the RC network comprised of R122
and C129. Once the voltage across C129 reaches 2V the DSP56301 will exit the reset state and read its
bootup program from the Boot PROM (U24, sheet 2). If the bootup procedure completes successfully then
the clock measured on R142 will be 66 MHz. If the DSP56301 failed to boot correctly this clock will be 3
MHz. After the DSP 56301 has completed its bootup procedure it waits for a startup program to be sent
through the PCI interface (P1, sheet 4). Upon receipt of this program from the host computer the DSP56301
programs the FPGA (U27, sheet 2). The DSP56301 programs the FPGA with the signals CCLK,
PROGRAM/, and FPGA_DIN. Once the FPGA has been programmed it turns on the FPGA_DONE LED
(labeled “A”). At this point the DSP56301 is running a program from its internal memory and LEDs “B” and
“C” are under software control.
DSP56301 (schematic sheet 1.)
The DSP56301 operates at 3.3V which is provided by a local regulator (U26, sheet 10). The DSP56301 is
clocked from an external 6 MHz crystal (Y1, sheet 1) and the on-chip PLL is used to generate a 66 MHz
clock.
The DSP 56301 provides an integrated interface to the PCI bus including all the configuration and address
mapping registers. Both PCI master and slave modes are used. The Core2 is a Universal PCI bus card,
which means that the card will operate in a 5V PCI signaling environment or a 3.3V PCI signaling
environment. This is accomplished by providing the PCI I/O power pins to the 56301 on a dedicated voltage
clamp pin (pin 137). The DSP 56301 integrates a 6-channel DMA controller that performs memory-to-
memory (including memory-mapped peripherals) transfers in parallel with other DSP operations. Some of
these channels are used to move samples between the PCI FIFOs to the DSP's internal memory while
other channels move samples to and from the FPGA.
The Core2 uses the DSP56301 timer 0 to measure the frequency of the audio sample clock. The signal
DSP_WCLK is sent from the FPGA to the DSP56301 for this purpose.
The DSP data and address buses are connected to the FPGA and are used to transmit audio samples
between the DSP56301 and the FPGA.
The DSP56301 has internal address decoders that are used to generate the AA0/, AA1/, and AA2/ chip
select signals. These address decodes are shown in the following five tables. The address decoder for
AA0/ is programmed differently for 48K/44.1K vs. 96K/88.2K mode.
DSP 56301 Expansion Port Memory Map (AA1, AA2 chip selects)
Chip Select Address Resource
AA2 $20000B SPDIF RX Channel Status byte 1
AA2 $20000A SPDIF RX Channel Status byte 0
AA2 $200009 SPDIF TX Channel Status byte 3
AA2 $200008 SPDIF TX Channel Status byte 0
AA2 $200007 not used
AA2 $200006 not used
AA2 $200005 A/D Right Channel Volume Control Register
AA2 $200004 A/D Left Channel Volume Control Register
AA2 $200003 System Status Register
AA2 $200002 Word Clock Phase Control Register
AA2 $200001 System Control Register 1
AA2 $200000 System Control Register 0
AA2 $D00400 - $FFFFFF not used
AA2 $D00000 - $D003FF Boot ROM Program