Lexicon CORE2, Service Manual

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Lexicon Studio Core2 Service Manual
Addendum #6: PUNCH ROUTING IN CUBASE ................................................................................... 5-5
Addendum #7: CLOCK SOURCE CONSISTENCY IN CUBASE ......................................................... 5-6
Addendum #8: THE EFFECT OF ROUTING CHANGES ON WAVE DRIVERS .................................. 5-6
Addendum #9: SELECTION OF WINDOWS SOUNDS........................................................................ 5-7
Addendum #10: CLOCK SOURCE SELECTION IN MMIO .................................................................. 5-7
Addendum #11: MMIO BUS ALIGNMENT IN ACID AND COOL EDIT PRO ....................................... 5-7
Addendum #12: NOISES THAT OCCUR AFTER SHUTDOWN OF SAMPLITUDE ............................ 5-7
Addendum #13: S/PDIF EFFECTS LOOP............................................................................................ 5-7
CORE2 USER'S GUIDE ERRATA........................................................................................................ 5-8
V1.20-P1 Update....................................................................................................................................... 5-8
Lexicon Studio Core2: Update patch v120-P1 won't unzip properly......................................................... 5-9
C2V120P2.reg - Update............................................................................................................................ 5-9
Lexicon Studio Core2: In Cubase®, the LexPanel does not get properly shut down from the task bar... 5-9
Chapter 6 Theory of Operation .................................................................. 6-1
Architectural Overview .............................................................................................................................. 6-1
Core2 Block Diagram ................................................................................................................................ 6-2
Startup Sequence ..................................................................................................................................... 6-3
DSP56301 (schematic sheet 1.) ............................................................................................................... 6-3
DSP 56301 Expansion Port Memory Map (AA1, AA2 chip selects) ......................................................... 6-3
DSP 56301 Expansion Port Memory Map (AA0 chip select, 48K/44.1K mode)....................................... 6-4
DSP 56301 Expansion Port Memory Map (AA0 chip select, 96K/88.2K mode 1).................................... 6-4
DSP 56301 Expansion Port Memory Map (AA0 chip select, 96K/88.2K mode 2).................................... 6-4
DSP 56301 Expansion Port Memory Map (AA0 chip select, 96K/88.2K mode 3).................................... 6-5
DSP 56301 ESSI Ports ............................................................................................................................. 6-5
DSP 56301 ESSI Port C Register............................................................................................................. 6-5
DSP 56301 ESSI Port D Register............................................................................................................. 6-5
XCS10 FPGA (schematic sheet 2.) .......................................................................................................... 6-5
System Control Register 0 ........................................................................................................................ 6-6
System Control Register 1 ........................................................................................................................ 6-6
Word clock source encoding..................................................................................................................... 6-6
System Status Register............................................................................................................................. 6-7
SPDIF TX Channel Status byte 3 ............................................................................................................. 6-7
SPDIF sample rate encoding .................................................................................................................... 6-7
Sample Clock Phase-Locked Loop (schematic sheet 3.) ......................................................................... 6-7
PCI & Option Connectors (schematic sheet 4.) ........................................................................................ 6-7
Audio I/O & Connectors (schematic sheet 5.)........................................................................................... 6-8
A/D Conversion (schematic sheet 6.) ....................................................................................................... 6-8
D/A Conversion (schematic sheets 8, 9 ).................................................................................................. 6-8
Voltage Regulators (schematic sheet 10.) ................................................................................................ 6-8
Chapter 7 - Parts List................................................................................. 7-1
CORE 2 PC BOARD ASSEMBLY ............................................................................................................ 7-1
CORE2 CONNECTOR BD MECHANICAL ASSEMBLY .......................................................................... 7-3
CORE 2 CONNECTOR BD PC BOARD ASSEMBLY .............................................................................. 7-3
CORE 2 SHIPPING MATERIAL ............................................................................................................... 7-3
Chapter 8 Schematics and Drawings......................................................... 8-1
Schematics:............................................................................................................................................... 8-1
Drawings: .................................................................................................................................................. 8-1