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© 2021 LeddarTech Inc.
6.4.
Block Diagrams
Power
Block
(see Power page)
H
e
at
er
(6
-p
in
)
(5
3
3
9
8
0
6
7
1
)
ARM
(TMS5700914APZQQ1)
MUX_P
DAC_SPI1CLK_1-4
LC
In
te
rfa
ce
c
o
n
n
e
ct
o
r
(2
0
-p
in
)
(2
0
35
6
4
20
1
7
)
Connectors
Integrated Circuit
Circuits with multiple components
Power
Digital
Analog
DAC_SPI1SIMO_1-4
DAC_SPI1SOMI_1-4
TMUX_SEL_A0
DAC2_nSYNC
DAC3_nSYNC
DAC4_nSYNC
nCLR_DAC
PWM_SEL_1
PWM_SEL_2
PWM_SEL_3
PWM_SEL_5
PWM_SEL_6
PWM_SEL_7
PWM_SEL_8
PWM_SEL_4
EXT_SPI_nCS0
EXT_SPI_CLK
EXT_SPI_SIMO
EXT_SPI_SOMI
1V2_MON
3V3_MON
24V_MON
30V_MON
VREF_MON
VBATT_REG_MON
3V0_VREF (6mA)
(ADC)
NEXT
FEEDBACK
RESET/START
UART_TX
UART_RX
1V2_PG
3V3_PG
I2C_SCL
I2C_SDA
24V_EN
60V_EN
PWM_ITO1
PWM_ITO3
PWM_ITO2
SW3 (Bootloader)
SW1
SW2
LED1
LED2
nOE_LVLTR
OSCIN
nPORRST
TCK
TDI
TDO
TMS
TRST_N
TEST
nERROR
OSCOUT
Kelvin_GND
16MHz
nRST
Supervisory
(TPS3808G01-Q1)
3V3_PG
1V2
Temp Sensor
(TMP100-Q1)
30V
(3x)
1V2_PG
3V3_PG
JT
A
G
(1
0
-p
in
)
(F
TS
H
-1
0
5-
01
-L
-DV
-K)
I2C_SCL
I2C_SDA
3V3
24V_EN
60V_EN
U
SB
(M
ic
ro
-B)
3V3
3V3
ITO_1P
ITO_2P
ITO_3P
Translator
(CAXC4T774-Q1)
Translator
(CAXC4T774-Q1)
3V0_VREF
1V2_MON
3V3_MON
24V_MON
30V_MON
VREF_MON
VBATT_REG_MON
1V2
3V3
24V
30V
3V0_VREF
VBATT_REG
FP
C
1
6
-p
in
(5
01
95
1
16
50
)
EXT_VREF
Dual DAC
(DAC7562-Q1)
Dual
Switch
(
TS3USB221A
-Q1
)
Dual Op-
Amp
(OPA2192-Q1
)
nLDAC
3V0_VREF
nLDAC
nCLR_DAC
DAC_SPI_CLK
DAC_SPI_SIMO
DACx_nSYNC
Dual
Switch
(
TS3USB221A
-Q1
)
PWM_SEL_x
PWM_SEL_x
Dual Op-
Amp
(OPA2192-Q1
)
Dual Op-
Amp
(OPA2376-Q1
)
Dual Op-
Amp
(OPA2376-Q1
)
FB_LCx_N
FB_LCx_P
FB_LCx_N
FB_LCx_P
DAC[4:1]_nSYNC
3V0_VREF
nLDAC
nCLR_DAC
DAC_SPI1SIMO
DAC_SPI1_CLK
(This circuit is
replicated 4 times)
PWM_SEL_[8:1]
8:1
(TMUX1208
QRSVRQ1)
8:1
(TMUX1208
QRSVRQ1)
FB_LC_P
FB_LC_N
ON
MUX_N
TESTPOINT1
TP1
TP2
FTDI
FT234XD
TMUX_SEL_A1
TMUX_SEL_A2
DAC1_nSYNC
I2C Buffer
(TCA9517-Q1)
TV
S
TV
S
TV
S
In
p
u
t
C
o
n
n
e
ct
o
r
(0
t
o
3
6
V
, 3
A
@
1
2
V
)
VBATT
3V3
1V2
24V
30V
3V0_VREF
24V_EN
30V_EN
3V3_PG
1V2_PG
TV
S
TV
S
TV
S
TV
S
TV
S
TVS
ESD
TV
S
TV
S
3V3_OUT_nEN
LCx_P
LCx_N
LCx_P
LCx_N
Dual
NPN
TV
S
TV
S
TV
S
TV
S
TV
S
TV
S
TV
S
TV
S
ECLK
ADEVT
H
e
a
d
e
r
4
-p
in
Op-Amp
(OPA376-Q1
)
3V0_VREF
COM_OFFSET
(0-500 mV)
Gain = 8
Gain = 8
Gain = 1/8
Gain = 1/8
Microcontroller
Power supply
Fig. 12: LeddarSteer EVB logical block diagram