C2000 Debugger | 28
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1989-2023
Lauterbach
The below offered selection options are all non-bufferable. Alternatively you can enter a <value>, where
value[5:4] determines the Domain bits and value[3:0] the Cache bits.
AXIAPn.ACEEnable
[
ON
|
OFF
]
SYStem.Option.AXIACEEn-
able
[
ON
|
OFF
]
(deprecated)
Default: OFF.
Enables ACE transactions on the AXI-AP, including barriers. This
does only work if the debug logic of the target CPU implements
coherent accesses. Otherwise this option will be without effect.
AXIAPn.CacheFlags
<value>
SYStem.Option.AXI-
CACHEFLAGS
<value>
(deprecated)
Default: DeviceSYStem (=0x30: Domain=0x3, Cache=0x0).
This option configures the value used for the Cache and Domain
bits in the Control Status Word (CSW[27:24]->Cache, CSW[14:13]-
>Domain) of an Access Port, when using the AXI: memory class.
<name>
Description
DeviceSYStem
=0x30: Domain=0x3, Cache=0x0
NonCacheableSYStem
=0x32: Domain=0x3, Cache=0x2
ReadAllocateNonShareable
=0x06: Domain=0x0, Cache=0x6
ReadAllocateInnerShareable
=0x16: Domain=0x1, Cache=0x6
ReadAllocateOuterShareable
=0x26: Domain=0x2, Cache=0x6
WriteAllocateNonShareable
=0x0A: Domain=0x0, Cache=0xA
WriteAllocateInnerShareable
=0x1A: Domain=0x1, Cache=0xA
WriteAllocateOuterShareable
=0x2A: Domain=0x2, Cache=0xA
ReadWriteAllocateNonShareable
=0x0E: Domain=0x0, Cache=0xE
ReadWriteAllocateInnerShareable
=0x1E: Domain=0x1, Cache=0xE
ReadWriteAllocateOuterShareable
=0x2E: Domain=0x2, Cache=0xE
