Lauterbach C2000 Manual Download Page 12

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C2000 Debugger | 12

1989-2023

Lauterbach

<parameter>

(JTAG cont.)

IRPOST

<bits>

IRPRE

<bits>

Slave

[

OFF

]

TAPState

<state>

TCKLevel

<level>

TriState

[

OFF

]

<parameter>

(MultiTap)

DAPTAP

<tap>

DEBUGTAP

<tap>

ETBTAP

<tap>

(C5000 only)

MULTITAP

[

NONE

IcepickA

IcepickB

IcepickC

IcepickD

IcepickBB

IcepickBC

IcepickCC

IcepickDD

JtagSEQuence

<sub_cmd>

]

NJCR

<tap>

SLAVETAP

<tap>

<parameter>

(AccessPorts
)

AHBAPn.Base

<address>

AHBAPn.HPROT

[

<value>

<name>

]

AHBAPn.Port

<port>

AHBAPn.RESet
AHBAPn.view
AHBAPn.XtorName

<name>

APBAPn.Base

<address>

APBAPn.Port

<port>

APBAPn.RESet
APBAPn.view
APBAPn.XtorName

<name>

AXIAPn.ACEEnable

[

OFF

]

AXIAPn.Base

<address>

AXIAPn.CacheFlags

<value>

AXIAPn.HPROT

[

<value>

<name>

]

AXIAPn.Port

<port>

AXIAPn.RESet
AXIAPn.view
AXIAPn.XtorName

<name>

DEBUGAPn.Port

<port>

DEBUGAPn.RESet
DEBUGAPn.view
DEBUGAPn.XtorName

<name>

JTAGAPn.Base

<address>

JTAGAPn.Port

<port>

JTAGAPn.CorePort

<port>

JTAGAPn.RESet
JTAGAPn.view
JTAGAPn.XtorName

<name>

Summary of Contents for C2000

Page 1: ...MANUAL Release 02 2023 C2000 Debugger...

Page 2: ...ses 9 DSP specific SYStem Commands 10 SYStem CONFIG state Display target configuration 10 SYStem CONFIG Configure debugger according to target topology 11 parameters describing the DebugPort 17 parame...

Page 3: ...andling 53 SYStem Option ExecutionMode Sets the CPU execution mode 54 SYStem Option IMASKASM Disable interrupts while single stepping 54 SYStem Option IMASKHLL Disable interrupts while HLL single step...

Page 4: ...C2000 Debugger 4 1989 2023 Lauterbach C2000 Debugger Version 10 Feb 2023 History 23 Nov 22 New command SYStem Option ExecutionMode...

Page 5: ...t of debug commands Architecture specific information Processor Architecture Manuals These manuals describe commands that are specific for the processor architecture supported by your Debug Cable To a...

Page 6: ...language similar to C that lets you create functions to extend Code Composer Studio s usefulness The converter allows you to convert GEL language into PRACTICE scripts cmm which can be used directly i...

Page 7: ...e target while the target power is off 2 Connect the host system the TRACE32 hardware and the Debug Cable 3 Power ON the TRACE32 hardware 4 Start the TRACE32 software to load the debugger firmware 5 C...

Page 8: ...and 100 s If a terminal window is open the response time of the trigger system is undefined It is recommended not to use the trigger system and terminal window at the same time Breakpoints Software Br...

Page 9: ...Memory Classes The following DSP specific memory classes are available To access a memory class write the class in front of the address Prepending an E as attribute to the memory class will make memo...

Page 10: ...b tab DebugPort Jtag MultiTap AccessPorts COmponents tab Opens the SYStem CONFIG state window on the specified tab For tab descriptions see below DebugPort default The DebugPort tab informs the debugg...

Page 11: ...ich memory bus and at which base address the debugger can find the control registers of the modules For descriptions of the commands on the COmponents tab see COmponents Format SYStem CONFIG parameter...

Page 12: ...meter AccessPorts AHBAPn Base address AHBAPn HPROT value name AHBAPn Port port AHBAPn RESet AHBAPn view AHBAPn XtorName name APBAPn Base address APBAPn Port port APBAPn RESet APBAPn view APBAPn XtorNa...

Page 13: ...view C5000 C6000 C7000 only parameter COmponents cont CMI Base address CMI RESet CMI TraceID id CMI view COREDEBUG Base address C7000 only COREDEBUG RESet C7000 only COREDEBUG view C7000 only CTI Base...

Page 14: ...EP ATBSource source REP Base address REP Name string REP RESet REP view SC Base address SC RESet SC TraceID id SC view STM Base address STM Mode None SDTI STP STP64 STPv2 STPv2LE STM Name string STM R...

Page 15: ...s ETBBASE address ETBFUNNELBASE address ETFBASE address ETMBASE address parameter Deprecated cont FUNNEL2BASE address FUNNELBASE address HTMBASE address ITMBASE address RTPBASE address SDTIBASE addres...

Page 16: ...on SYStem CPU type to become active and it might additionally depend on further settings Ideally you can select with SYStem CPU the chip you are using which causes all setup you need and you do not ne...

Page 17: ...d might be required in a multicore environment if you use multiple debugger instances multiple TRACE32 PowerView GUIs to simultaneously debug different cores on the same target system Because of the d...

Page 18: ...gCa bleA DebugCableB It specifies which probe cable shall be used e g DebugCableA or DebugCableB At the moment only the CombiProbe allows to connect more than one probe cable Default depends on detect...

Page 19: ...ck on the SWCLK line is stopped kept low You can configure the debugger to pull the SWDIO data line high when no operation is in progress by using SYStem CONFIG SWDPIdleHigh ON Default OFF SWDPTargetS...

Page 20: ...ber of TAPs in the JTAG chain between the TDI signal and the TAP you are describing In BYPASS mode each TAP contributes one data register bit See possible TAP types and example below Default 0 DRPRE b...

Page 21: ...ble 0 Exit2 DR 1 Exit1 DR 2 Shift DR 3 Pause DR 4 Select IR Scan 5 Update DR 6 Capture DR 7 Select DR Scan 8 Exit2 IR 9 Exit1 IR 10 Shift IR 11 Pause IR 12 Run Test Idle 13 Update IR 14 Capture IR 15...

Page 22: ...mory access changes the JTAG chain and the core TAP position then you can specify the new values with the NEXT parameter After the access for example the parameter NEXTIRPRE will replace the IRPRE val...

Page 23: ...C2000 Debugger 23 1989 2023 Lauterbach...

Page 24: ...s different versions Icepickx STCLTAPx MSMTAP Example DAPTAP tap Specifies the TAP number which needs to be activated to get the DAP TAP in the JTAG chain Used if MULTITAP Icepickx DEBUGTAP tap Specif...

Page 25: ...ialize the MSMTAP Please note some of these parameters need a decimal input dot at the end IcepickXY means that there is an Icepick version X which includes a subsystem with an Icepick of version Y Fo...

Page 26: ...specially important if the core you intend to debug is connected to such an internal JTAG interface The module controlling these JTAG interfaces is called JTAG Access Port JTAG AP Each JTAG AP can con...

Page 27: ...sed for the HPROT bits in the Control Status Word CSW of a CoreSight AXI Access Port when using the AXI memory class MEMORYAPn HPROT value name Default 0 This option selects the value used for the HPR...

Page 28: ...x3 Cache 0x0 This option configures the value used for the Cache and Domain bits in the Control Status Word CSW 27 24 Cache CSW 14 13 Domain of an Access Port when using the AXI memory class name Desc...

Page 29: ...XtorName name APB bus transactor name identifying the bus where the debug register can be found Used for DAP access class MEMORYAPn XtorName name AHB bus transactor name identifying the bus where syst...

Page 30: ...ss Default port not available DEBUGAPn Port port DEBUGACCESSPORT port deprecated AP access port number 0 255 of a SoC 400 system where the debug register can be found typically on APB Used for DAP acc...

Page 31: ...FIG APBAP1 Base DP 0x80003000 Meaning The control register block of the APB access ports starts at address 0x80003000 AXIAPn Base address This command informs the debugger about the start address of t...

Page 32: ...race components your chip includes and which you intend to use with the debugger s help Each configuration can be done by a command in a script file as well Then you do not need to enter everything ag...

Page 33: ...n most cases Example SYStem CONFIG COREDEBUG Base 0x80010000 0x80012000 SYStem CONFIG BMC Base 0x80011000 0x80013000 SYStem CONFIG ETM Base 0x8001c000 0x8001d000 SYStem CONFIG STM1 Base EAHB 0x2000800...

Page 34: ...e the interconnection by ATBSource source A CoreSight trace FUNNEL has eight input ports port 0 7 to combine the data of various trace sources to a common trace stream Therefore you can enter instead...

Page 35: ...exists only for FUNNELs For a list of possible components including a short description see Components and Available Commands BASE address This command informs the debugger about the start address of...

Page 36: ...ug on a certain chip You will loose trace data at the end of the recording Don t use it if not needed Default OFF RESet Undo the configuration for this component This does not cause a physical reset f...

Page 37: ...om and to the CTIs ARMv8 only ARMV8V3 Channel 0 1 and 2 of the CTM are used to distribute start stop events Implemented on request ARMv8 only ETB Size size Specifies the size of the Embedded Trace Buf...

Page 38: ...just a number which you need to figure out in the chip documentation RTP PerBase address PERBASE specifies the base address of the core peripheral registers which accesses shall be traced PERBASE is n...

Page 39: ...Enables trace to be stored in a dedicated SRAM The trace data will be read out through the debug port after the capturing has finished FUNNEL ATBSource sourcelist FUNNEL Base address FUNNEL Name stri...

Page 40: ...ring statistic data about bus traffic to a system trace module STM Base address STM Mode NONE XTIv2 SDTI STP STP64 STPv2 STM RESet STM Type None Generic ARM SDTI TI System Trace Macrocell STM MIPI ARM...

Page 41: ...ssible via APB bus In an SMP Symmetric MultiProcessing debug session you can enter for the components BMC CORE CTI ETB ETF ETM ETR a list of base addresses to specify one component per core Example as...

Page 42: ...d Available Commands CTICONFIG type Informs about the interconnection of the core Cross Trigger Interfaces CTI Certain ways of interconnection are common and these are supported by the debugger e g to...

Page 43: ...NEL2PORT port FUNNEL2 ATBSource DTM port 1 DTMFUNNELPORT port FUNNEL1 ATBSource DTM port 1 DTMTPIUFUNNELPORT port FUNNEL3 ATBSource DTM port 1 DWTBASE address DWT Base address ETB2AXIBASE address ETB2...

Page 44: ...ess SDTIBASE address STM1 Base address STM1 Mode SDTI STM1 Type SDTI STMBASE address STM1 Base address STM1 Mode STPV2 STM1 Type ARM STMETBFUNNELPORT port FUNNEL4 ATBSource STM1 port 1 STMFUNNEL2PORT...

Page 45: ...nostic module SYStem CPU Select the used CPU Default selection C280X Selects the processor type TRACEFUNNELPORT port FUNNEL1 ATBSource ADTF port 1 TRACETPIUFUNNELPORT port FUNNEL3 ATBSource ADTF port...

Page 46: ...window Besides a decimal number like 100000 short forms like 10kHz or 15MHz can also be used The short forms imply a decimal value although no is used CTCK With this option higher JTAG speeds can be...

Page 47: ...he need to synchronize the processor clock and the JTAG clock In this case RTCK shall be selected Synchronization is maintained because the debugger does not progress to the next TCK edge until after...

Page 48: ...ich do not have a fixed name for the memory access method Denied default Real time memory access during program execution to target is disabled Format SYStem Mode mode SYStem Attach alias for SYStem M...

Page 49: ...o be in DOWN state when switching to this mode It resets and starts the program when power is detected Halt the program execution and set all the breakpoints and trace conditions you need then re star...

Page 50: ...13 Domain of an AXI Access Port of a DAP when using the AXI memory class SYStem Option AXIHPROT Select AXI AP HPROT bits Default 0 This option selects the value used for the HPROT bits in the Control...

Page 51: ...recommended that SYStem Option DAPDBGPWRUPREQ is set to AlwaysON SYStem Option DAPNOIRCHECK No DAP instruction register check Default OFF Bug fix for derivatives which do not return the correct patte...

Page 52: ...ange address NOTE Up to 16 address_range address pairs are possible Each pair has to contain an address range followed by a single address Format SYStem Option DAPSYSPWRUPREQ AlwaysON ON OFF AlwaysON...

Page 53: ...listed below This is the default Normally it does not hurt to try improper switching sequences Therefore this succeeds in most cases None There is no switching sequence required The SW DP is ready af...

Page 54: ...Disable interrupts while HLL single stepping Default OFF If enabled the interrupt mask bits of the CPU will be set during HLL single step operations The interrupt routine is not executed during single...

Page 55: ...ctivates a more powerful error handling This option should be used if the debugger shows any unstable behavior SYStem RESetOut Reset target without reset of debug port If possible nRESET is open colle...

Page 56: ...mmands TrOnchip state Display on chip trigger window Opens the TrOnchip state window TrOnchip RESet Set on chip trigger to default state Sets the TrOnchip settings and trigger module to the default se...

Page 57: ...additional hardware breakpoints as well as benchmark counters BMC general_ref_b pdf If an application running on the device needs to access the ERAD module the ERAD has to be turned off in TRACE32 ER...

Page 58: ...s connector This is a standard 20 pin double row connector pin to pin spacing 0 100 in We strongly recommend to use a connector on your target with housing and having a center polarization e g AMP 2 8...

Page 59: ...input It is connected to the supply translating transceiver nSRST nRESET is used by the debugger to reset the target CPU or to detect a reset on the target It is driven by an open collector buffer A 4...

Page 60: ...C2000 Debugger 60 1989 2023 Lauterbach Mechanical Description of the TI Connector FAQ Please refer to https support lauterbach com kb...

Page 61: ...C2000 Debugger 61 1989 2023 Lauterbach Operation Voltage Adapter OrderNo Voltage Range JTAG Debugger for C2000 DSP ICD LA 7847 1 8 3 6 V...

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