C2000 Debugger | 11
©
1989-2023
Lauterbach
SYStem.CONFIG
Configure debugger according to target topology
AccessPorts
This tab informs the debugger about an Arm CoreSight Access Port (AP)
and about how to control the AP to access chip-internal memory busses
(AHB, APB, AXI) or chip-internal JTAG interfaces.
For a descriptions of a corresponding commands, refer to
.
COmponents
The
COmponents
tab informs the debugger (a) about the existence and
interconnection of on-chip CoreSight debug and trace modules and (b)
informs the debugger on which memory bus and at which base address
the debugger can find the control registers of the modules.
For descriptions of the commands on the
COmponents
tab, see
Format:
SYStem.CONFIG
<parameter>
SYStem.MultiCore
<parameter>
(deprecated)
<parameter>
:
CJTAGFLAGS
<flags>
(C7000 only)
CONNECTOR
[
MIPI34
|
MIPI20T
] (C7000 only)
CORE
<core> <chip>
CoreNumber
<number>
DEBUGPORT
[
DebugCable0
|
DebugCableA
|
DebugCableB
]
DEBUGPORTTYPE
[
JTAG
|
SWD
|
CJTAG
]
Slave
[
ON
|
OFF
]
SWDP
[
ON
|
OFF
] (C7000 only)
SWDPIdleHigh
[
ON
|
OFF
]
SWDPTargetSel
<value>
TriState
[
ON
|
OFF
]
<parameter>
:
DAPDRPOST
<bits>
DAPDRPRE
<bits>
DAPIRPOST
<bits>
DAPIRPRE
<bits>
DRPOST
<bits>
DRPRE
<bits>
ETBDRPOST
<bits>
(C5000 only)
ETBDRPRE
<bits>
(C5000 only)
ETBIRPOST
<bits>
(C5000 only)
ETBIRPRE
<bits>
(C5000 only)
