6
LatticeMico32/DSP Development Board
Lattice Semiconductor
User’s Guide
Table 2. Audio Codec U1001 Pin Definitions
The signal CODEC CS# has a pull-up resistor of 10 k
Ω
. The Signal CODEC MODE selects the interface to use for
the codec. Driving it high corresponds to SPI, low to I
2
C.
Detailed information on the audio codec can be found at the Texas Instruments web site at www.ti.com.
Clock Sources
A 25 MHz oscillator supplies the FPGA (primary clock pin A10 and PLL input V1), the MachXO (pin A8), the Ether-
net controller and the Expansion Connector (pin 29 of X12). The frequency can be measured via testpoint CLK. A
25MHz input clock is required by the Ethernet controller. To generate other clock frequencies, use the PLLs of the
FPGA. You can find detailed information for the usage of the PLLs on the Lattice web site and in the LatticeECP/EC
Family Data Sheet.
The USB controller requires a 24 MHz quartz oscillator for configuration. Another 12 MHz quartz supplies the USB
host/peripheral controller.
DDR SODIMM Socket for DDR SDRAM Modules
The board includes a standard DDR1 SODIMM socket with 200 contacts (DDR SDRAM Module is not included).
The upper four bytes of the data bus are not connected. Thus, only half of the capacity of the memory module is
available.
The DDR SODIMM socket is factory configured to provide a regulated 2.5V. DDR400 modules require a power
supply of 2.6V (±0.1V). To support DDR400, you must short-circuit pins 2 and 3 of connector X18. Position 1-2 is
used for 2.5V mode. If you have your board in front of you so that the power supply is in the upper left corner, pin 1
is the right-most one and is marked with a copper etched triangle
.
Note:In bank 2, there are four DQSs. Two of them do not have the required DQ pins available. Therefore, only two
DDR interfaces are valid. So, the LatticeECP33 can have a 16-bit DDR interface
.
Pin
Signal Name
FPGA Pin
Pin
Signal Name
FPGA Pin
3
CODEC BCLK
W1
21
CODEC CS#
W4
4
CODEC DIN
W2
6
CODEC DOUT
W3
5
CODEC LRCIN
AA1
7
CODEC LRCOUT
Y2
25
CODEC MCLK
Y3
24
CODEC SCLK
Y1
23
CODEC SDIN
AA2
22
CODEC MODE
V4
Table 3. DDR SODIMM Socket (X4) - Data Bus, n.c. ... Not Connected
Pin
Signal Name
FPGA Pin
Pin
Signal Name
FPGA Pin
11
DDR DQS0
A16
47
DDR DQS2
H18
12
DDR DM0
B15
48
DDR DM2
H19
5
DDR DQ0
A14
41
DDR DQ16
D21
7
DDR DQ1
B14
43
DDR DQ17
F20
13
DDR DQ2
A15
49
DDR DQ18
G21
17
DDR DQ3
B16
53
DDR DQ19
G20
6
DDR DQ4
A17
42
DDR DQ20
H20
8
DDR DQ5
B17
44
DDR DQ21
J19
14
DDR DQ6
A18
50
DDR DQ22
J18
18
DDR DQ7
B18
54
DDR DQ23
H17
25
DDR DQS1
D21
61
DDR DQS3
J20
26
DDR DM1
D21
62
DDR DM3
K20
