Lattice Semiconductor LatticeMico32/DSP User Manual Download Page 21 | Manualshive

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21

LatticeMico32/DSP Development Board

Lattice Semiconductor

User’s Guide

Table 24. Interface Between the MachXO and the FPGA

FPGA

The LFECP33 represents the heart of the board. It has the following features:

• 32.8 k Look-Up Tables (LUTs)

• 131 kbit distributed RAM

• 498 kbit EBR SRAM

• 54 EBR SRAM blocks

• Four PLLs

• 360 user I/Os available

• DDR memory support (DDR400)

• Supported I/O standards: LVCMOS, LVTTL, SSTL, HSTL, LVDS

The ispLEVER design software can be used to develop/modify programs for the FPGA using Verilog or VHDL
design entry methods. For more information on the ispLEVER software, see www.latticesemi.com/software.

Sample programs for the FPGA are available on-line as well. These can be found at www.latticesemi.com/boards.
Select

FPGA/FPSC Boards -> LatticeMico32/DSP Development board

and click on the

Design Files

link.

For further information please consult the LatticeECP/EC Family Data Sheet.

Parallel Flash

Two parallel MX29LV128MBTI-90Q Flash components from Macronics are provided on the board for program code
and data. As with the SRAM, a 32-bit data bus is realized with these two devices. Thus, Flash can be accessed as
a 8Mx32 memory. The 23-bit address bus, the data bus and the control signals are connected directly to the FPGA

.

SPI Flash

The LatticeECP33 FPGA is an SRAM-based programmable device, and is therefore volatile. In order for it to be
automatically configured upon power-up, a non-volatile 8 Mbit SPI Flash device is provided. The SPI Flash can be
programmed with configuration bitstream data. The SPI Flash can be configured either through the ispDOWN-
LOAD connector or via the integrated USB configuration interface.

Important Note:

The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-

LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG
pins. Failure to follow these procedures can in result in damage to the LatticeECP2 FPGA device and render the
board inoperable.

To program the SPI Flash configuration device, use the FPGA Loader function of the ispVM System software. The
FPGA Loader programming scheme provides an in-system JTAG programming method for configuration devices.
The FPGA acts as a bridge between the JTAG interface and the SPI interface of the serial configuration device.

Configure the SPI Flash as follows:

1.

In the ispVM System software, choose

Edit -> Add Device

to open the Device Information dialog box.

MachXO Pin

Signal Name

MachXO Pin

MachXO Pin

Signal Name

MachXO Pin

A1

MACHXO IO0

C1

A2

MACHXO IO1

E2

A3

MACHXO IO2

F3

B3

MACHXO IO3

R6

A4

MACHXO IO4

U3

C4

MACHXO IO5

V3

A5

MACHXO IO6

V2

C8

MACHXO CLK

B1

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Summary of Contents for LatticeMico32/DSP

Page 1: ...October 2007 Revision EB17_01 4 LatticeMico32 DSP Development Board User s Guide ...

Page 2: ...LOAD cable for programming the FPGA Flywire connector for programming using an ispDOWNLOAD cable available separately 9 pin RS232 serial port 230 Kbps 15 pin VGA 64 color encoding Ethernet 10 100 M full half duplex Two USB 2 0 compatible host connectors One USB 2 0 compatible target connector One USB OTG On the Go connector Expansion connector with 46 user I Os 12x12 prototyping area for the integ...

Page 3: ...number of example and demonstration programs are available for the LatticeMico32 DSP Development board Check the Lattice web site at www latticesemi com boards and navigate to the correct board to find additional documentation and design and programming files Note Unless described otherwise positional statements left right etc refer to the board positioned in front of you so that the key pad is in...

Page 4: ...d the LED7SegsTest project The LED7SegsTest mem and LED7SegsTest bit files are included in the LED7SegsTest project Visual indications of operation are Left to Right and Right to Left scanning of the 8 LEDs Upcount and roll over of the 7 segment displays from 0 to 99 decimal at 1 second intervals LCD Backlight X5 Jumper Open Backlight is off Configuration Switch TMS Switch Off Down LatticeECP33 de...

Page 5: ... audio codec TLV320AIC23BIPW from Texas Instruments LCD Contrast Potentiometer Microphone Input Audio Line In Line Out LCD Connector X6 Ethernet 10 100M 3 3V Testpoint 2 5V Testpoint GND Testpoint 1 2V Testpoint CLK Testpoint Flywire Connector X3 High Speed USB for Configuration DIP Switch for the Configuration X5 X13 X12 Expansion Connector DDR SDRAM Socket X4 USB Host Connector Mini USB OTG Conn...

Page 6: ...ata bus are not connected Thus only half of the capacity of the memory module is available The DDR SODIMM socket is factory configured to provide a regulated 2 5V DDR400 modules require a power supply of 2 6V 0 1V To support DDR400 you must short circuit pins 2 and 3 of connector X18 Position 1 2 is used for 2 5V mode If you have your board in front of you so that the power supply is in the upper ...

Page 7: ... DQ31 L19 Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 112 DDR A0 D16 111 DDR A1 C16 110 DDR A2 E15 109 DDR A3 D15 108 DDR A4 C15 107 DDR A5 E14 106 DDR A6 D14 105 DDR A7 C14 102 DDR A8 E13 101 DDR A9 D13 115 DDR A10 E16 100 DDR A11 C13 99 DDR A12 B13 123 DDR A13 C17 117 DDR BA0 E17 116 DDR BA1 D17 Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 35 DDR CK0 B12 37 DDR CK0 A12 160 DDR CK1 A20...

Page 8: ...14 15 EXPCON IO40 U13 16 EXPCON IO41 U12 17 EXPCON IO42 U11 18 EXPCON IO43 V14 19 EXPCON IO44 V13 20 EXPCON IO45 W13 21 VCC5V0 22 GND 23 VCC2V5 24 GND 25 VCC3V3 26 GND 27 VCC3V3 28 GND 29 EXPCON OSC 30 GND 31 EXPCON CLKIN 32 GND 33 EXPCON CLKOUT 34 GND 35 VCC3V3 36 GND 37 VCC3V3 38 GND 39 VCC3V3 40 GND Table 8 Expansion Connector X13 Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 1 HPE RESET 2 ...

Page 9: ...m the Lattice web site at www latticesemi com ispvm Note Do not change the switch when the configuration of a device is in progress Note The board as configured from the factory has a built in USB ispDOWNLOAD cable The built in cable and an external ispDOWNLOAD cable cannot be used at the same time Table 9 ispDOWNLOAD Connector X3 Pin Definition High Speed LVDS Connector On the right side of the b...

Page 10: ... Table 11 LCD Connector X6 Pin Definition Serial Interface The board includes an RS232 serial interface port The interface provides transmit TX receive RX and hard ware handshaking The MAXIM MAX3232 data sheet provides detailed information on the interface circuit A 9 pin female to 9 pin female null modem cable is required Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin 1 HSCON DAT0 E21 2 HSCON ...

Page 11: ...USB Host Peripheral Controller U0702 This controller is compliant with the Universal Serial Bus Specification 2 0 You can transmit and receive serial data at both full speed 12 Mbps and low speed 1 5 Mbps data rates For more information please refer to the data sheet of the USB controller U0703 and U0704 are USB power control switches which must be enabled by the user via the USB PWEN signals The ...

Page 12: ...ly use the built in ispDOWNLOAD cable or an external ispDOWNLOAD cable exclusively It is not recommended to switch between cables without first power cycling the board Failure to follow this recommenda tion may cause unpredictable results and may possibly damage the board Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin U0703 1 USB PWEN0 B2 U0703 2 USB OC0 E1 U0703 4 USB PWEN1 C2 U0703 3 USB OC1 ...

Page 13: ...rstand the SYNC frequencies of the VGA monitor being connected to the VGA plug and adjust the FPGA frequencies as required Table 16 VGA Connector X1B Pin Definition n c Not Connected Figure 5 VGA Connector 56 GP CTL2 C2 51 GP CTL3 C1 52 GP CTL4 B2 76 GP CTL5 B1 23 GP T0 M2 24 GP T1 N1 25 GP T2 P1 28 GP BKPT F12 100 USB CLK O M7 26 GP IFCLK M8 41 GP RXD0 E13 40 GP TXD0 E14 43 GP RXD1 F13 42 GP TXD1...

Page 14: ...he position of the user interface elements Figure 6 User Interface Features 2 5 V LED green 3 3 V LED green FPGA Configuration LED blue FPGA Initialization LED red Single Step Key Reset Key 3 x 4 Keyboard 7 Segment Display 8 LEDs with Testpads LCD Connector Program Key Program LED yellow 4 x DIP Switches ...

Page 15: ... DIP Switches There is a 4 bit DIP switch on the board When the switch is turned to the on position a logic 1 will be seen The connections are in Table 18 Table 18 DIP Switches SW0514 Connection LEDs Eight LEDs can be used for custom status signaling They are low active with a logic 0 the LED is on You can control the LEDs via the signals below Table 19 LED LD0501 LD0508 Connection Pin Signal Name...

Page 16: ...ix You do not need the polling method if only four keys are used Connect the column driver signals of one column to VCC the other two to GND and query the row data signals CPU Reset Key The CPU reset key is a global reset Please refer to the Reset Chip section of this document for detailed informa tion Single Step Key The single step key is connected to a normal input of the FPGA and can be used b...

Page 17: ...Figure 8 illustrates the position of major components Figure 8 Components Ethernet PHY Asynchronous SRAM SPI Flash MachXO Audio Codec USB Controller USB Controller for the Configuration 8 x 6 Prototyping Area of the MachXO Parallel Flash 12 x 12 Prototyping Area of the FPGA FPGA LFEC33 ...

Page 18: ...GA Connections for the 12x12 Prototyping Area FPGA Pin Signal Name LRF Pin FPGA Pin Signal Name LRF Pin AB13 BB3V3 IO0 TP0901 AB12 BB3V3 IO1 TP0902 AA12 BB3V3 IO2 TP0903 Y12 BB3V3 IO3 TP0904 W12 BB3V3 IO4 TP0905 V12 BB3V3 IO5 TP0906 V11 BB3V3 IO6 TP0907 U10 BB3V3 IO7 TP0908 T10 BB3V3 IO8 TP0909 U9 BB3V3 IO9 TP0910 T9 BB3V3 IO10 TP0911 U8 BB3V3 IO11 TP0912 AB10 BB3V3 CLK0 TP0918 AB11 BB3V3 CLK0 TP0...

Page 19: ...O2 BB3V3_IO1 BB3V3_IO0 BB3V3_IO4 BB3V3_IO5 BB3V3_IO6 BB3V3_IO7 BB3V3_IO8 BB3V3_IO9 BB3V3_IO10 BB3V3_IO11 BB2V5_IO0 BB2V5_IO 9 0 BB2V5_IO1 BB2V5_IO2 BB2V5_IO3 BB2V5_IO4 BB2V5_IO6 BB2V5_IO7 BB2V5_IO8 BB2V5_IO9 BB2V5_IO5 BB2V5_DAT0 BB2V5_DAT0 VCC3V3 GND VCC2V5 TP09104 TP0935 TP0996 TP0912 TP0963 TP09124 TP0954 TP09117 TP0944 TP0908 TP09106 TP0936 TP0921 TP0964 TP0986 TP09125 TP0957 TP09115 TP0946 TP0...

Page 20: ...ilt in download cable permits the FPGA and SPI PROM to be programmed It is not recommended for the MachXO to be repro grammed However the MachXO does provide some connections to the LatticeECP33 FPGA and to an 8x6 proto typing area For further information please consult the MachXO Family Data Sheet GND TP0343 GND TP0344 GND TP0345 GND TP0346 GND TP0347 GND TP0348 Table 23 MachXO Connections for th...

Page 21: ...d directly to the FPGA SPI Flash The LatticeECP33 FPGA is an SRAM based programmable device and is therefore volatile In order for it to be automatically configured upon power up a non volatile 8 Mbit SPI Flash device is provided The SPI Flash can be programmed with configuration bitstream data The SPI Flash can be configured either through the ispDOWN LOAD connector or via the integrated USB conf...

Page 22: ... Loader 12 If desired select Hardware Setup to display general information about the configuration process 13 Click OK to exit the FPGA Loader add the devices and return to the ispVM System software window 14 Click GO The ispVM System software programs the SPI Flash via the FPGA 15 Disconnect and then reconnect the power supply The FPGA will take about three seconds to be programmed by the SPI Fla...

Page 23: ...e board was shipped you can alternatively unplug the power supply and then plug it in again Table 25 Pin Table Pin Name Signal Name Appliance F21 HS DAT2 High speed LVDS Connector E22 HS DAT2 High speed LVDS Connector F11 BB2V5 IO0 FPGA Prototyping Area F12 BB2V5 IO1 FPGA Prototyping Area F13 BB2V5 IO2 FPGA Prototyping Area G13 BB2V5 IO3 FPGA Prototyping Area F14 BB2V5 IO4 FPGA Prototyping Area G1...

Page 24: ...o Codec Y2 CODEC LRCOUT Audio Codec Y3 CODEC MCLK Audio Codec V4 CODEC MODE Audio Codec Y1 CODEC SCLK Audio Codec AA2 CODEC SDIN Audio Codec V21 CSSPIN Configuration U7 DAC DIG DAC D16 DDR A0 DDR RAM C16 DDR A1 DDR RAM E16 DDR A10 DDR RAM C13 DDR A11 DDR RAM B13 DDR A12 DDR RAM C17 DDR A13 DDR RAM E15 DDR A2 DDR RAM D15 DDR A3 DDR RAM C15 DDR A4 DDR RAM E14 DDR A5 DDR RAM D14 DDR A6 DDR RAM C14 DD...

Page 25: ...R RAM A15 DDR DQ2 DDR RAM H20 DDR DQ20 DDR RAM J19 DDR DQ21 DDR RAM J18 DDR DQ22 DDR RAM H17 DDR DQ23 DDR RAM F22 DDR DQ24 DDR RAM G22 DDR DQ25 DDR RAM H22 DDR DQ26 DDR RAM H21 DDR DQ27 DDR RAM K19 DDR DQ28 DDR RAM K18 DDR DQ29 DDR RAM B16 DDR DQ3 DDR RAM L18 DDR DQ30 DDR RAM L19 DDR DQ31 DDR RAM A17 DDR DQ4 DDR RAM B17 DDR DQ5 DDR RAM A18 DDR DQ6 DDR RAM B18 DDR DQ7 DDR RAM B22 DDR DQ8 DDR RAM B2...

Page 26: ...3 Ethernet J4 ETH RXDV Ethernet J5 ETH RXER Ethernet J1 ETH TXCLK Ethernet H1 ETH TXD0 Ethernet H2 ETH TXD1 Ethernet H3 ETH TXD2 Ethernet H4 ETH TXD3 Ethernet J3 ETH TXEN Ethernet J2 ETH TXER Ethernet U20 EXPCON CLKIN Expansion Connector Y22 EXPCON CLKOUT Expansion Connector K22 EXPCON IO0 Expansion Connector K21 EXPCON IO1 Expansion Connector N22 EXPCON IO10 Expansion Connector N21 EXPCON IO11 Ex...

Page 27: ...Connector AB21 EXPCON IO35 Expansion Connector T17 EXPCON IO36 Expansion Connector T14 EXPCON IO37 Expansion Connector T13 EXPCON IO38 Expansion Connector U14 EXPCON IO39 Expansion Connector L20 EXPCON IO4 Expansion Connector U13 EXPCON IO40 Expansion Connector U12 EXPCON IO41 Expansion Connector U11 EXPCON IO42 Expansion Connector V14 EXPCON IO43 Expansion Connector V13 EXPCON IO44 Expansion Conn...

Page 28: ...D B1 MACHXO CLK0 Configuration C1 MACHXO IO0 Configuration E2 MACHXO IO1 Configuration F3 MACHXO IO2 Configuration R6 MACHXO IO3 Configuration U3 MACHXO IO4 Configuration V3 MACHXO IO5 Configuration V2 MACHXO IO6 Configuration V1 CLK FPGA Clock AB20 MEMORY A0 FLASH SRAM AA20 MEMORY A1 FLASH SRAM AA17 MEMORY A10 FLASH SRAM Y17 MEMORY A11 FLASH SRAM W17 MEMORY A12 FLASH SRAM V17 MEMORY A13 FLASH SRA...

Page 29: ...H SRAM AA9 MEMORY DQ18 FLASH SRAM Y9 MEMORY DQ19 FLASH SRAM V15 MEMORY DQ2 FLASH SRAM W9 MEMORY DQ20 FLASH SRAM V9 MEMORY DQ21 FLASH SRAM AB8 MEMORY DQ22 FLASH SRAM AA8 MEMORY DQ23 FLASH SRAM Y8 MEMORY DQ24 FLASH SRAM W8 MEMORY DQ25 FLASH SRAM V8 MEMORY DQ26 FLASH SRAM AB7 MEMORY DQ27 FLASH SRAM AA7 MEMORY DQ28 FLASH SRAM Y7 MEMORY DQ29 FLASH SRAM U15 MEMORY DQ3 FLASH SRAM W7 MEMORY DQ30 FLASH SRA...

Page 30: ...ion V22 SPIDO Configuration AB4 SRAM BE0 FLASH SRAM AA4 SRAM BE1 FLASH SRAM AB3 SRAM BE2 FLASH SRAM AA3 SRAM BE3 FLASH SRAM Y4 SRAM CE FLASH SRAM U4 TST COL0 Key Matrix U6 TST COL1 Key Matrix V5 TST COL2 Key Matrix T1 TST ROW0 Key Matrix T2 TST ROW1 Key Matrix T3 TST ROW2 Key Matrix R1 TST ROW3 Key Matrix V6 TST STEP Key Matrix E6 USB CTS USB B7 USB GPIO0 USB C7 USB GPIO1 USB F8 USB GPIO10 USB A9 ...

Page 31: ...B B8 USB GPIO6 USB C8 USB GPIO7 USB D8 USB GPIO8 USB E8 USB GPIO9 USB C4 USB MISO USB D3 USB MOSI USB E1 USB OC0 USB D1 USB OC1 USB D2 USB OC2 USB B2 USB PWEN0 USB C2 USB PWEN1 USB C3 USB PWEN2 USB D6 USB RTS USB D5 USB RXD USB C6 USB SCK USB C5 USB SSI USB D4 USB TXD USB A5 VGA BL0 VGA B6 VGA BL1 VGA A4 VGA GR0 VGA B5 VGA GR1 VGA A7 VGA HSYNC VGA A3 VGA RD0 VGA B4 VGA RD1 VGA A6 VGA VSYNC VGA Tab...

Page 32: ...RDQS40 ExpCon_IO 4 ExpCon_IO 3 ExpCon_IO 2 L M RS_CTS0_ TTL RS_RXD0_ TTL SEG _A SEG _B SEG _C VCC 1 2V VCC 3 3V VCC 3 3V GND GND GND GND GND GND VCC 3 3V VCC 3 3V VCC 1 2V ExpCon_IO 9 ExpCon_IO 8 ExpCon_IO 7 ExpCon_IO 6 ExpCon_IO 5 M N SEG _D SEG _E SEG _F SEG _G SEG _DP VCC 1 2V VCC 1 2V VCC 3 3V GND GND GND GND GND GND VCC 3 3V VCC 1 2V VCC 1 2V ExpCon_IO 14 ExpCon_IO 13 ExpCon_IO 12 ExpCon_IO 1...

Page 33: ...nformation herein are subject to change without notice Portions copyright 2005 2006 Gleichmann and Company Electronics GmbH Description Ordering Part Number China RoHS Environment Friendly Use Period EFUP LatticeMico32 DSP Development Board LFECP33E D EV ispLEVER Base with LatticeMico32 DSP Development Kit LS ECP33 BASE PC N Date Version Change Summary July 2006 01 0 Initial release March 2007 01 ...

Page 34: ...LASH_RESET 4 HPE_RESET 3 6 EXPCON_IO 45 0 3 9 USB_MISO 7 USB_SSI 7 USB_SCK 7 USB_MOSI 7 USB_TXD 7 DDR_CKE0 4 DDR_BA0 4 DDR_BA1 4 DDR_VREF 4 DDR_WE 4 DDR_RAS 4 DDR_CAS 4 DDR_S0 4 DDR_S1 4 DDR_DQ 31 0 4 DDR_A 13 0 4 DDR_CK0 4 DDR_CK0 4 DDR_DQS 3 0 4 DDR_DM 3 0 4 DDR_CK1 4 CODEC_MODE 10 USB_RXD 7 USB_RTS 7 USB_CTS 7 MACHXO_IO 6 0 3 MACHXO_CLK0 3 DDR_CKE1 4 DDR_CK1 4 HSCON_DAT1 9 HSCON_DAT1 9 HSCON_DA...

Page 35: ...02 0R00 1 2 TP0342 TP0346 100n C0314 12p0 C0340 RJ0303 nb_10K0 1 2 TP0320 1n00 C0301 RJ0305 nb_10K0 1 2 LD0301 LED blue 100n C0316 100n C0319 TP0304 X2 USB Peripheral VCC 1 DATA 2 DATA 3 GND 4 SHIELD 5 SHIELD 6 100n C0312 R0307 4k70 1 2 TP0326 R0317 10K0 1 2 SW0302 CAS 120A A 1 B 3 C 2 TP0311 Q0301 24MHz 1 2 TP0359 T0302 BSS138 SOT FB0301 BLM18BD601SN1 1 2 TP0344 TP0353 TP0350 RJ0301 nb_10K0 1 2 1...

Page 36: ...C3V3 GND GND GND VCC3V3 VCC3V3 GND GND VCC3V3 VCC3V3 MEMORY_A 22 0 2 MEMORY_DQ 31 0 2 FLASH_RESET 2 FLASH_RY BY _A 2 FLASH_RY BY _B 2 SRAM_BE0 2 SRAM_BE1 2 SRAM_BE2 2 SRAM_BE3 2 SRAM_CE 2 MEMORY_OE 2 MEMORY_WE 2 FLASH_CE 2 FLASH_WP ACC 2 FLASH_BYTE 2 DDR_DQ 31 0 2 DDR_A 13 0 2 DDR_CK0 2 DDR_CK0 2 DDR_DQS 3 0 2 DDR_DM 3 0 2 DDR_CK1 2 DDR_CK1 2 DDR_CKE0 2 DDR_CKE1 2 DDR_BA0 2 DDR_BA1 2 DDR_WE 2 DDR_...

Page 37: ...e Display Contrast TP0507 nb_TEST POINT 1 R0523 1K00 1 2 SW0514 SW DIP 4 LD0502 LED red R0507 330R 1 2 R0510 100K TP0508 nb_TEST POINT 1 SW0502 B3FS 1010P 1 3 2 4 LD0507 LED red R0501 330R 1 2 D0506 MMBD4148 SW0504 B3FS 1010P 1 3 2 4 D0508 MMBD4148 D0510 MMBD4148 D0512 MMBD4148 R0522 120R 1 2 TP0509 nb_TEST POINT 1 RP0502 10K0 1 8 2 7 3 6 4 5 D0501 MMBD4148 SW0508 B3FS 1010P 1 3 2 4 R0502 330R 1 2...

Page 38: ...t c e j o r P Authors Revision Created Last modified IFW o f Page t e s e R _ k c o l C _ 6 0 12 6 Ext Reset Reset Button Reset Control Clock Sources 1 25 V Rp of the I2C bus Rs of the I2C bus CLK Offpage Vth 1 25V x R0601 R0602 R0602 4 4V R0614 33R0 SW0601 B3FS 1010P 1 3 2 4 FB0601 BLM21PG331SN1D 1 2 R0611 22R0 100n C0601 TP0601 TEST POINT 1 U0601 CAT1026SI 30 VLOW 1 RESET 2 VSENSE 3 GND 4 SDA 5 ...

Page 39: ...Hz USB OTG USB HOST USB HOST USB HOST C0707 1u00 100n C0701 EXT MEMORY EXT MEMORY CONTROL GPIO USB PORTS CHARGE PUMP RESET CLOCK POWER U0702 CY7C67300_TQFP100 A1 1 A2 2 A4 7 A3 3 A6 17 A5 8 A8 24 A9 25 A7 20 A10 27 A11 30 A12 31 A13 32 A14 33 A15 CLKSEL 38 A16 97 A17 95 A18 96 D0 83 A0 BEL 99 D1 82 D2 81 D3 80 D4 79 D5 78 D6 77 D7 76 D8 MISO 74 D9 SSI 73 D10 SCK 72 D11 MOSI 71 D12 TXD 70 D13 RXD 6...

Page 40: ...0810 49R9 1 2 C0806 1n00 1 2 R0808 49R9 1 2 R0816 22K1 1 2 R0801 220R 1 2 R0813 220R 1 2 R0802 22R0 1 2 C0801 270p 1 2 C0802 270p 1 2 R0805 nb_10K0 1 2 R0818 10K0 1 2 R0804 nb_10K0 1 2 C0810 220n 1 2 LED0801 LED red 1 2 RJ0805 nb_10K0 1 2 C0805 10n0 1 2 RJ0803 nb_10K0 1 2 R0809 49R9 1 2 C0809 220n 1 2 U0802 PULSE H1112 RD 5 RD 6 CT_RD 4 TD 1 TD 2 CT_TD 3 RX 8 RX 7 CT_RX 9 TX 12 TX 11 CT_TX 10 R080...

Page 41: ..._IO 45 0 2 3 BB3V3_CLK0 2 BB3V3_CLK0 2 BB2V5_IO 7 0 2 HSCON_DAT4 2 HSCON_DAT4 2 HSCON_DAT1 2 HSCON_DAT1 2 HSCON_DAT2 2 HSCON_DAT2 2 HSCON_DAT0 2 HSCON_DAT0 2 HSCON_DAT3 2 HSCON_DAT3 2 t e e h S t c e j o r P Authors Revision Created Last modified IFW o f Page C p x E _ 9 0 on_ProtoArea 12 9 Offpage Expansion Connector Prototyping Area RM2 54 of FPGA Pin 2 removed for coding of expansion board LVDS...

Page 42: ...2 VGA_HSYNC 2 VGA_BL1 2 VGA_VSYNC 2 CODEC_MODE 2 t e e h S t c e j o r P Authors Revision Created Last modified IFW o f Page 10_Audio_VGA 12 10 Audio Codec MICIN LINEIN LINEOUT VGA Interface Offpage Interface Mode 0 1 2 wire SPI 10u0 C1011 47p0 C1005 470n C1004 R1007 4k70 1 2 R1005 4k70 1 2 R1018 270R R1002 100R 1 2 R1012 270R R1009 10K0 1 2 470n C1003 R1013 270R RJ1002 nb_10K0 1 2 1u00 C1012 47p0...

Page 43: ...02 TEST POINT 1 L1103 10u0 R1111 0R05 1 2 D1103 10MQ040N 1 2 LD1102 LED green 10u0 C1101 SI6966DQ T1101A 4 1 2 3 220p C1118 optional Pad1102 ArtNr05281 LD1101 LED green D1104 MBR0540LT1 1 2 nb_10n0 C1125 R1114 330R 1 2 C1130 220u optional Pad1101 ArtNr05281 optional Pad1105 ArtNr05281 R1107 15K0 1 2 4p70 C1132 D1101 MBR0540LT1 1 2 SI6966DQ T1102A 4 1 2 3 R1108 15K0 1 2 100n C1124 SI6966DQ T1101B 5...

Page 44: ...iceMico32 DSP Development Board Lattice Semiconductor User sGuide Appendix B Assembly Diagram Note Figures 23 26 provide an enlargement of each numbered section in Figure 22 Figure 22 Assembly Diagram 1 2 3 4 ...

Page 45: ...45 LatticeMico32 DSP Development Board Lattice Semiconductor User sGuide Figure 23 Assembly Diagram Section 1 Detail ...

Page 46: ...46 LatticeMico32 DSP Development Board Lattice Semiconductor User sGuide Figure 24 Assembly Diagram Section 2 Detail ...

Page 47: ...47 LatticeMico32 DSP Development Board Lattice Semiconductor User sGuide Figure 25 Assembly Diagram Section 3 Detail ...

Page 48: ...48 LatticeMico32 DSP Development Board Lattice Semiconductor User sGuide Figure 26 Assembly Diagram Section 4 Detail ...

Page 49: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Lattice LS ECP33 BASE PC N ...

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