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LatticeMico32/DSP Development Board
Lattice Semiconductor
User’s Guide
12 x 12 FPGA Prototyping Area of The FPGA
A 12x12 prototyping area is available on the right side of the board. The lead-wire spacing of the prototyping area
is 100mil (2.54 mm). Figure 10 shows the prototyping area in top view. 14 plated-through-holes on its left side are
connected to the FPGA. Eight through-holes on the right side are wired to a 2.5V I/O bank. In the top row of the
prototyping area there are six connections to the 3.3V power supply as well as three to 2.5V. The bottom row has
ten plated-through-holes connected to GND.
Table 22. FPGA Connections for the 12x12 Prototyping Area
FPGA Pin
Signal Name
LRF Pin
FPGA Pin
Signal Name
LRF Pin
AB13
BB3V3 IO0
TP0901
AB12
BB3V3 IO1
TP0902
AA12
BB3V3 IO2
TP0903
Y12
BB3V3 IO3
TP0904
W12
BB3V3 IO4
TP0905
V12
BB3V3 IO5
TP0906
V11
BB3V3 IO6
TP0907
U10
BB3V3 IO7
TP0908
T10
BB3V3 IO8
TP0909
U9
BB3V3 IO9
TP0910
T9
BB3V3 IO10
TP0911
U8
BB3V3 IO11
TP0912
AB10
BB3V3 CLK0+
TP0918
AB11
BB3V3 CLK0-
TP0919
F11
BB2V5 IO0
TP09133
F12
BB2V5 IO1
TP09134
F13
BB2V5 IO2
TP09135
G13
BB2V5 IO3
TP09136
F14
BB2V5 IO4
TP09137
G14
BB2V5 IO5
TP09140
F15
BB2V5 IO6
TP09141
F16
BB2V5 IO7
TP09142
—
VCC3V3
TP0913
—
VCC3V3
TP0925
—
VCC3V3
TP0937
—
VCC3V3
TP0949
—
VCC3V3
TP0961
—
VCC3V3
TP0973
—
VCC2V5
TP0997
—
VCC2V5
TP09109
—
VCC2V5
TP09121
—
GND
TP0924
—
GND
TP0936
—
GND
TP0948
—
GND
TP0960
—
GND
TP0972
—
GND
TP0984
—
GND
TP0996
—
GND
TP09108
—
GND
TP09120
—
GND
TP09132